Publications (11)4.53 Total impact

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    J. H. Park · S.-W. Kim · J. H. Kim · D.-H. Ko · Z. Wu · S. L. Cho · D. Ahn · D. H. Ahn · J. M. Lee · S. W. Nam
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    ABSTRACT: In this study, we propose a nitrogen-incorporated GeBiTe ternary phase of N7.9(Ge46.9Bi7.2Te45.9) as a phase change material for reliable PCM (Phase Change Memory) with high speed operation. We found that the N7.9(Ge46.9Bi7.2Te45.9) film shows the resistance value of 40 kΩ after annealing at 440oC for 10 minutes, which is much higher than the value of 3.4 kΩ in the case of conventional N7.0(Ge22.0Sb22.0Te56.0) films. A set operation time of 14 nsec was achieved in the devices due to the increased probability of the nucleation by the addition of the elemental Bi. The long data retention time of 10 years at 85oC on the base of 1% failure was obtained as the result of higher activation energy of 2.52 eV for the crystallization compared to the case of N7.0(Ge22.0Sb22.0Te56.0) film, in which the activation energy is 2.1 eV. In addition, a reset current reduction of 27% and longer cycles of endurance as much as 2 order of magnitude compared to the case of N7.0(Ge22.0Sb22.0Te56.0) were observed at a set operation time of 14 nsec. Our results show that N7.9(Ge46.9Bi7.2Te45.9) is highly promising for use as a phase change material in reliable PCMs with high performance and also in forthcoming storage class memory applications, too.
    Preview · Article · Aug 2015 · AIP Advances
  • J. H. Park · S.-W. Kim · J. H. Kim · Z. Wu · S. L. Cho · D. Ahn · D. H. Ahn · J. M. Lee · S. U. Nam · D.-H. Ko
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    ABSTRACT: Phase Change Memory (PCM) has been proposed for use as a substitute for flash memory to satisfy the huge demands for high performance and reliability that promise to come in the next generation. In spite of its high scalability, reliability, and simple structure, high writing current, e.g., RESET current, has been a significant obstacle to achieving a high density in storage applications and the low power consumption required for use in mobile applications. We report herein on an attempt to determine the level of carbon incorporated into a GeSbTe (GST) film that is needed to reduce the RESET current of PCM devices. The crystal structure of the film was transformed into an amorphous phase by carbon doping, the stability of which was enhanced with increasing carbon content. This was verified by the small grain size and large band gap that are typically associated with carbon. The increased level of C-Ge covalent bonding is responsible for these enhancements. Thus, the resistance of the carbon doped Ge 2Sb2Te5 film was higher than that for an undoped GST film by a factor of 2 orders of magnitude after producing a stable face-centered cubic phase by annealing. As a consequence, the PCM devices showed a significant reduction in RESET current as low as 23% when the carbon content was increased to 11.8 at. %. This can be attributed to the elevated SET resistance, which is proportional to the dynamic resistance of the PCM device, caused by the high resistance due to a carbon doped GST film.
    No preview · Article · Mar 2015 · Journal of Applied Physics
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    ABSTRACT: A PRAM cell with great scalability and high speed operation capability with excellent reliability below 20nm technology was demonstrated. This has the meaning of the potential applicable to the technology area of scaling limitation of DRAM cell. We fabricated a confined PRAM cell with 7.5nm×17nm of below 4F<sup>2</sup>. In particular, Sb-rich Ge-Sb-Te phase change material was employed for high speed operation below 30nsec. The excellent writing endurance performance was predicted to maintain up to 6.5E15cycles by reset program energy acceleration. Its data retention was 4.5 years at 85°C which is enough for DRAM application.
    Full-text · Conference Paper · Jul 2010
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    ABSTRACT: We present a new-type confine structure within 7.5 nm width dash-contact for sub 20 nm generation PRAMs. Phase change material (PCM) by chemical vapor deposition (CVD) was perfectly filled in a 7.5 nm width dash-contact without void along with 30 nm depth. By adopting confined CVD-PCM, we were able to reduce the reset current below ~160 muA and to obtain high reliability. In addition, the programming time of dash-confined cell was much improved to 50 ns due to volume confinement of PCM cell. Consequently, we firstly demonstrate the high performance of the 7.5 nm width confined cell, which is the smallest size close to physical limit.
    Full-text · Conference Paper · Jan 2009
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    ABSTRACT: first present a PRAM with confinement of chemically vapor deposited GeSbTe (CVD GST) within high aspect ratio 50 nm contact for sub 50 nm generation PRAMs. By adopting confined GST, we were able to reduce the reset current below ~260 muA and thermally stable CVD Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub> compound having hexagonal phase was uniformly filled in a contact while maintaining constant composition along with 150 nm depth. Our results indicate that the confined cell structure of 50 nm contact is applicable to PRAM device below 50 nm design rule due to small GST size based on small contact and direct top electrode contact, reduced reset current, minimized etch damage, and low thermal disturbance effect.
    No preview · Conference Paper · Jul 2007
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    ABSTRACT: We firstly fabricated on-axis confined structure and evaluated based on 64Mb PRAM with 0.12μm-CMOS technologies. Ge<sub>2</sub>Sb<sub>2</sub>Te <sub>5</sub> was confined within small pore, which resulted in low writing current of 0.4mA. The pore is on-axis with upper and lower contacts, which leads to good scalability of PRAM above 256Mb. The confined structure was relatively insensitive to small cell edge damage effect. The on-axis confined structure is a promising candidate for high density PRAM due to low writing current, good scalability, and insensitiveness to edge damage.
    No preview · Conference Paper · Jul 2005
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    ABSTRACT: A novel 8F<sup>2</sup> cell structure for high density magnetic random access memory (MRAM) and its operating characteristics are proposed. In this new scheme, we formed bottom electrode contact (BEC) through twin metal lines (MLs) and a magnetic tunnel junction (MTJ) was located just on the BEC for the reduction of cell size. From the results of simulation and experiment, we have confirmed that the generated magnetic field in the new scheme is more uniform than that in the conventional scheme with a negligible reduction of writing field strength. We adopted a self-aligned BEC process to prevent electrical shorting between ML and BEC. To avoid electrical shorting and improve the magnetic properties of MTJs, a chemical mechanical polishing (CMP) process was adopted before MTJ deposition. As a result, we confirmed the feasibility of high-density 1T1MTJ MRAM, composed of 8F<sup>2</sup> cells with optimal MTJ characteristics.
    No preview · Conference Paper · Jan 2004
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    ABSTRACT: Novel capacitor technologies for high density FRAM device with 0.18 μm D/R (design-rule) have been researched and developed. In order to realize the high-density FRAM device with 0.18 μm D/R, the PZT film was modified by changing Zr/Ti composition and by using PTO seeding layer. Therefore, the crystallization temperature of the PZT film could be successfully lowered to 550°C. The remnant polarization of PTO-used 100 nm thick PZT capacitors measured at 2.7 V was approximately 24 μC/cm, that is 30% higher than that of the PTO-unused PZT capacitors. Necessarily, as the PZT thickness and crystallization temperature are lowered, the thickness of bottom electrode can be reduced as well. Furthermore, by lowering the PZT crystallization temperature and by applying robust TiAlN oxidation barrier, low (300 Ω/contact) and stable contact resistance in a very small size of BC could be obtained. Finally, we successfully developed a capacitor stack height of 270 nm. The capacitor size was 0.26 × 0.44 μm and remnant polarization measured at 2.7 V was approximately 11 μC/cm.
    No preview · Article · Jan 2004 · Ferroelectrics
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    ABSTRACT: Effects of the PbTiO 3 (PTO) seeding layer on lowering the PZT crystallization temperature and reducing the capacitor stack height, especially PZT thin film, were systematically investigated. For these purposes, PZT film was modified by using the PTO seeding layer. By using the PTO seeding layer; the crystallization temperature of the PZT film was successfully lowered to 550°C. And remanant polarization of PTO-used 100nm thick PZT capacitors measured at 3V was approximately 23 w C/cm 2 , that is 30% higher than that of the PTO-unused PZT capacitors. XRD analysis indicated that the use of the PTO seeding layer remarkably increased the relative intensity of (111) orientation. XRF studies showed that the atomic concentration ratio of Ti-to-Zr was increased by using PTO seeding layers. Necessarily, as the PZT thickness and crystallization temperature are lowered, the thickness of bottom electrode can be reduced as well. Finally, we successfully developed a capacitor stack height of below 400nm, which was composed of Ir/IrO 2 /PZT/Pt/IrO 2 . Furthemore, by lowering the PZT crystallization temperature, small (600 z /contact) and stable contact resistance in a very small size of BC could be obtained.
    No preview · Article · Jan 2002 · Integrated Ferroelectrics
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    S L Cho · H Horii · J H Park · J H Yi · B J Kuh · Y H Ha · S O Park · H S Kim · U I Chung · J T Moon
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    ABSTRACT: We have integrated a phase change random access memory (PRAM), completely based on 0.24µm-CMOS technologies using nitrogen doped GeSbTe films. The Ge 2 Sb 2 Te 5 (GST) thin films are well known to play a critical role in writing current of PRAM. Through device simulation, we found that high-resistive GST is indispensable to minimize the writing current of PRAM. For the first time, we found the resistivity of GST film can be controlled with nitrogen doping. Doping nitrogen to GST film successfully reduced writing current. A 0.24µm PRAM using N-doped GST films were demonstrated with writing pulse of 0.8mA-50ns for RESET and 0.4mA-100ns for SET. Also, the cell endurance has been enhanced with grain growth suppression effect of dopant nitrogen. Endurance performance of fully integrated PRAM using N-doped GST shows no fail bit up to 2E9 cycles. Allowing 1% failures, extrapolation to 85 o C indicates retention time of 2years. All the results show that PRAM is one of the most promising candidates in the memory market for the next generation memories.
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    D H Ahn · S L Cho · H Horii · D H Im · I.-S Kim · G H Oh · S O Park · M S Kang · S W Nam · C H Chung
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    ABSTRACT: Key factors and possible technologies to realize the high performance scalable PRAM has been discussed. Current features of PRAM as a NVM are insufficient to satisfy the high performance applications to be opened in near future. In this paper, we consider the new process technology to overcome the limitation of current PRAM in terms of cell structure, phase change material, reliability and multi-bit strategy. Newly designed dash confined cell structure with doped-SbTe by ALD process is successfully demonstrated. It shows 30ns set program speed and good reliability performances with the predictable endurance of over 2e12 cycles and data retention of 4.5 years at 85℃ which is enough for computing applications. On the other hand, MLC technologies such as PMC and 3-cell reference concept with write and verify is promising for high density and cheaper PRAM. New solutions suggested in this paper, will enlarge the application variety and can open the new market.
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