[Show abstract][Hide abstract] ABSTRACT: Reliability of 32-nm-node ultralow-k (k=2.4)/Cu multilevel interconnects incorporating a bilayer low-k barrier cap (k=3.9) was improved without excessive wiring resistance by using CuAl seed technology with high-temperature and short-time annealing. Though the increase in wiring resistivity was about 10%, both electromigration (EM) and stress-induced voiding (SiV) reliability was clearly improved by using Cu-0.5 wt%Al seed metal.
[Show abstract][Hide abstract] ABSTRACT: We investigated tradeoff characteristics between resistivity and reliability for scaled-down Cu-based interconnects. A unique resistivity-measurement technique is proposed to detect influences due to impurity doping. Using this technique, we investigated the impacts of the impurity doping on three types of copper interconnects - cobalt-tungsten-phosphorous (CoWP) metal-cap interconnects, plasma-enhanced chemical-vapor-deposition self-aligned barrier interconnects, and CuAl alloy interconnects - and clarified the tradeoffs between the resistivity and the reliability. We found that the metal-cap interconnect shows not only high reliability but also outstanding efficiency with regard to the suppression of resistance increase due to impurity doping.
No preview · Article · Feb 2008 · IEEE Transactions on Electron Devices
[Show abstract][Hide abstract] ABSTRACT: A novel resistivity measurement technique has been proposed for scaled-down Cu interconnects viewing the high-reliability automobile applications. This technique enables to detect the interconnect resistivity dependence on impurity concentration, free from dimension dependence. Using this technique, we investigated impacts of impurity concentration on three types of Cu interconnects: 1) CoWP cap; 2) PECVD self-aligned barrier (PSAB); and 3) CuAl interconnects and clarified the tradeoffs between resistivity and reliability. We have found that CoWP cap shows not only high-reliability but also an outstanding efficiency in suppression of resistance increase due to impurity-induced scattering, indicating that it is the most viable candidate for automobile applications in 32nm generation and beyond
[Show abstract][Hide abstract] ABSTRACT: Electromigration (EM)-derived, void-nucleation and its growth have been investigated in 65-nm node, dual damascene interconnects (DDIs), and the effects of impurity-doping as well as adhesion-strength to SiCN-capping layer (CAP) are discussed regarding the EM-reliability improvement. It is found that reductive surface-treatment of Cu line improves the adhesion to the SiCN-CAP, elongating the incubation time of voiding at the via-bottom. The Al-doping is effective in suppressions both of the void nucleation and the growth, or the drift velocity. Consequently, the Al-doped, dilute Cu-alloy with the strong interface of the Cu/CAP improves the EM lifetime by 50 times refer to that of the conventional pure-Cu. Blocking all migration paths in Cu DDIs is essential for the EM-reliability improvement in 65nm-node LSIs and beyond
[Show abstract][Hide abstract] ABSTRACT: Molecular-pore-stacking (MPS), SiOCH films (k=2.4) are integrated in 45nm-node Cu interconnects with 140nm-pitched lines and 70nm-vias, and the feasibility is confirmed. The MPS film, which is deposited by plasma-polymerization of robust ring-type siloxane molecules, has the self-organized, porous structure with reinforcing the mechanical properties. The low permittivity is sustained in the 140nm-pitched lines by oxidation-damage-free etching, and the inter-line dielectric reliability is confirmed along with the BCB pore-seal technique, estimating 15.9% reduction in the 70nm-spaced, line capacitance refer to that of the 65nm-node SDIs. The MPS/Cu interconnect is one of the strong candidates for 45nm-node ULSI devices.