Yehia Massoud

Worcester Polytechnic Institute, Worcester, Massachusetts, United States

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Publications (220)92.85 Total impact

  • Shuang Li · Sami Smaili · Yehia Massoud
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    ABSTRACT: Integrated dc-dc converters are widely used for the realization of power converters suitable for energy harvesting and computing systems. In such systems, integrated converters are the ideal candidate due to their small size and low power consumption. Integrated dc-dc converters typically use spiral inductors to achieve high levels of integration and performance. However, under scenarios where energy scarcity is paramount, the integrated converter with spiral inductor requires careful modeling and optimization to achieve maximum efficiency. In this paper, we provide a parasitic aware design technique that takes into account the spiral inductor resistance as well as the switching parasitics, while utilizing numerical methods, to arrive at converter designs with robust performance and optimal efficiency. We translate the various system constraints into design rules and use them to formulate the various design parameters, from switching frequency to duty cycle, in terms of the inductance. We study how these parameters are dependent on each other, giving rise to multiple tradeoffs. We also present a method for minimizing power losses using optimization techniques, which leverage our formulation of the system parameters in terms of inductance.
    No preview · Article · Dec 2015 · IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Yang-Guo Li · Mohammad Rafiqul Haider · Yehia Massoud
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    ABSTRACT: Implantable wireless neural recording microsystems have demonstrated their efficacies in neuroscience studies in the past decades. However, with the advances of neurobiology, higher sensitivity and higher precision neural recording microsystems are becoming the critical need. A biopotential amplifier is the first stage of a neural recording microsystem, the performance of which decides the signal-to-noise ratio and the power dissipation of each recording-channel. In this paper, we present a low-noise biopotential amplifier with a noise efficiency factor (NEF) optimized closer to the theoretical limit of a folded cascode structure. A high transconductance input nMOSFET pair is designed to guarantee a low input-referred noise. A self-biased scheme comprising a weak positive feedback and a strong negative feedback is employed to further enhance the transconductance. By optimizing the noise performance while maintaining the NEF value close to the theoretical limit, a very low input-referred noise and a higher power-noise efficiency are achieved in our design. Using a standard 0.13-μm CMOS process, the proposed amplifier achieves an input-referred noise of 1.98 μVrms at the expense of 7.5 μW power, corresponding to a NEF of 2.31. The gain of the proposed amplifier is 40.84 dB at a -3 dB bandwidth from 6.65 Hz to 9.38 kHz.
    No preview · Article · May 2015 · Journal of Circuits System and Computers
  • Sami Smaili · Yehia Massoud
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    ABSTRACT: In this letter, we propose a new approach to reconfigurable receivers using random acquisition techniques. Random projections have been widely used within the context of compressive sensing for sub-Nyquist signal acquisition. In the system we propose, we design the random sensing signals so as to filter undesired components in the signal and result in measurements equivalent to those obtained had the signal been filtered prior to acquisition. Because the random signals are digitally generated, the system is reconfigurable; the signal's components to be filtered can be changed by changing the digitally generated random signals. The system digitizes the measurements at a rate proportional to the desired bandwidth only, not the total signal bandwidth.
    No preview · Article · Dec 2014 · IEEE Wireless Communication Letters
  • S. Smaili · Y. Massoud
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    ABSTRACT: Memristor memories provide non-volatile and high density solutions that can overcome some of the challenges faced by CMOS technology. Memristor memories use the memristor as a resistor and depict a logic 1 by a high resistance state and a logic 0 by a low resistance state. Typically, the memristor's resistance range is divided in half, and a state falling in the lower half depicts a logic 0 and the higher half depicts a logic 1. We show in this paper that it is better to use an unequal division of the range to define the resistance state corresponding to a given logic state. We show how this division can be optimized to provide the highest noise margin.
    No preview · Article · Nov 2014
  • Yang-Guo Li · Yehia Massoud · Mohammad Rafiqul Haider
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    ABSTRACT: A spike detector has become a necessity of a contemporary multichannel neural recording microsystem for data-compression. This paper proposes two spike detection algorithms, frequency-enhanced nonlinear energy operator (fNEO) and energy-of-derivative (ED), to solve the sensitivity degradation suffered by the conventional nonlinear energy operator (NEO) at the presence of large-amplitude baseline interferences. The efficiency of NEO, fNEO and ED algorithms are evaluated with Simulink programs firstly and then implemented into three low-power spike detectors with a standard 0.13-mu m CMOS process. To achieve a low-power design, subthreshold CMOS analog multipliers, derivatives and adders are developed to work with a low supply voltage, 0.5 V. The power dissipation of the proposed fNEO spike detector and ED spike detector are only 258.7 and 129.4 nW, respectively. The quantitative investigation shown in the paper indicates that both fNEO and ED spike detectors achieves superior performance than the conventional NEO spike detector. Considering its lowest power dissipation, the ED spike detector is selected for our application. Further statistical evaluations based on the true positive and false positive detection rate proves that the ED spike detectors achieves higher detection rate than that of the conventional NEO spike detector but dissipates 48 % less power.
    No preview · Article · Sep 2014 · Analog Integrated Circuits and Signal Processing
  • Sami Smaili · Yehia Massoud
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    ABSTRACT: The continuous demand for high storage capacities in modern electronic systems has made it more than ever important to find memory technologies beyond CMOS that are able to cope with the challenges at the nanoscale while catering to the requirements of high performance and robust operation. Memristors are excellent candidates for post CMOS memories, owing to their nanoscale nature and their programmability and ability to retain their state when turned off. In this paper we present design considerations for memristor memories for robust operation and discuss the trade-off between reading operations, refresh rates, and writing, stemming from the inherent variability of the memristor state when read.
    No preview · Conference Paper · Aug 2014
  • Sami Smaili · Yehia Massoud
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    ABSTRACT: Random demodulation provides a hardware-compact architecture for realizing compressive sensing systems. A random demodulator is realized by a mixer, with a random signal as the oscillator, and a low pass filter. In order to recover the original signal from the compressive sensing measurements, accurate modeling of the hardware components is needed. Typically, the reconstruction model assumes the low pass filter to be an ideal integrator. While this assumption is valid at low frequencies, it poses tremendous challenges at frequencies higher than 50MHz. In this paper, we provide an accurate and efficient model for the random demodulator that takes into account the actual structure of the filter. Using our model at reconstruction allows random demodulation for bandwidths extending to the GHz range, while, as we demonstrate, assuming an ideal integrator at reconstruction severely limits the system bandwidth.
    No preview · Conference Paper · Jun 2014
  • Yehia Massoud · Shuang Li · Sami Smaili
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    ABSTRACT: Integrated DC-DC converters are widely used in the realization of power converters suitable for energy harvesting and computing systems. In such systems, spiral inductors are typically used to achieve high levels of integration and perfor-mance. However, the integrated converter with spiral inductor requires careful modeling and optimization to achieve maximum efficiency. In this paper, we provide a parasitic aware design technique that takes into account the spiral inductor resistance as well as the switching parasitics, utilizing numerical techniques in order to yield designs that meet the desired performance requirements.
    No preview · Conference Paper · Jun 2014
  • Sami Smaili · Yehia Massoud
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    ABSTRACT: In this paper, we study the effect of filter variability in compressive sensing systems. Compressive sensing entails projecting the signal on a set of random signals, which is done by means of mixers and low pass filters. When reconstructing the signal, it is important to have a model for the sensing hardware, hence, the need to mitigate variability effects on the reconstruction process. In order to do that, there is a need for quantifying the effect of variability on reconstruction in order to be able to design compressive sensing systems that are robust to variability.
    No preview · Conference Paper · Jun 2014
  • Sami Smaili · Yehia Massoud
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    ABSTRACT: In this paper we derive conditions for bounding the state change in a memristor due to an applied signal. The main memristor functionality is a programmable resistor, but its resistance changes due to the signal passing through it. Therefore, it is necessary to guarantee that any signal through the memristor causes a small resistance change as tolerable by the application. The derived conditions relate the desired bound on the resistance change to a bound on the signal flux through the memristor. We show examples for the case of a sinusoidal signal and demonstrate the impact of the derived conditions on the design of memristor-based systems.
    No preview · Conference Paper · Jun 2014
  • Sami Smaili · Yehia Massoud
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    ABSTRACT: In this paper we propose and analyze the multichannel random demodulator, a compressive sensing system employing multiple random demodulation channels. This system fills the gap between a single channel system, the random demodulator, and an M channel system, which acquires one measurement per channel. The trade-off for changing the number of channels involves hardware efficiency and compactness. We provide an analysis of this trade-off and study the performance of the multi-channel random demodulator.
    No preview · Conference Paper · Jun 2014
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    ABSTRACT: Meeting the pressing power and bandwidth requirements of modern communication systems requires the development of highly efficient reconfigurable transceivers. On the receiver side, we present a new class of reconfigurable receiver that utilizes random projections to balance the power-bandwidth tradeoff. Such random projection front-ends are ubiquitous and allow the use of sub-Nyquist ADCs. These systems utilize high speed DACs, typically found in transmitters, to generate high fidelity random signals. The emergence of RF-DACs, used for direct digital-to-RF synthesis, can be leveraged for random projection reconfigurable receivers. However, the need for high output power and linearity in both the transmitter and receiver DACs forces an evaluation of RF-DAC topologies with respect to drain efficiency. In this paper, the power efficiencies of several RF-DAC topologies are compared.
    No preview · Conference Paper · Jun 2014
  • Yang-Guo Li · Mohammad Rafiqul Haider · Yehia Massoud
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    ABSTRACT: Due to their orthogonality and nearly constant pulse widths, Modified Hermite Pulses (MHPs) have shown a great potential to enhance the data rate of UWB communications by creating M-ary or multiple access parallel systems. However, the potential high power dissipation required by the pulse set generation and the frequency shifting has limited their utilization in practice. In this paper, we propose a novel computation-efficient model for MHP set generators. Compared with existing models, the proposed model has made it feasible to design a power-efficient MHP set generator. Utilizing our proposed model along with neuromorphic circuit level implementations, we have developed an ultra-low power architecture for MHP set generation for sub-GHz (0 - 960 MHz) UWB communications. Results from both the mathematical analysis and the design layout simulations illustrate the effectiveness of the proposed scheme for the design of a power-efficient MHP set generator.
    No preview · Conference Paper · Jun 2014
  • Sami Smaili · Yehia Massoud
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    ABSTRACT: The use of memristors as nanoscale programmable resistors allows the realization of compact tunable analog components such as tunable gain amplifiers. However, since the memristor's resistance depends on the signal through it, the design of such tunable memristor-based components should account for this memristor resistance change. In this paper, we analyze the effect of the memristor resistance change on the gain of the differential pair amplifier and demonstrate its dependence on the amplifier parameters and the signal frequency.
    No preview · Conference Paper · Aug 2013
  • Source
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    ABSTRACT: Spike detectors are important data-compression components for state-of-the-art implantable neural recording microsystems. This paper proposes two improved spike detection algorithms, frequency-enhanced nonlinear energy operator (fNEO) and energy-of-derivative (ED), to solve the sensitivity reduction of a conventional nonlinear energy operator (NEO) in the presence of baseline interference. The proposed methods are implemented in two analog spike detectors with a standard 0.13-μm CMOS process. To achieve an ultra-low-power design, weak-inversion MOSFET based multipliers, adders and derivative circuits are developed to work with a 0.5 V power supply. The power dissipations of the proposed fNEO spike detector and the ED spike detector are 258.7 nW and 129.4 nW, respectively. Quantitative investigations based on the standard deviation and peak-to-clutter ratio of the detected spikes indicate that the proposed spike detector schemes hold higher sensitivity than the conventional NEO based spike detector.
    Full-text · Conference Paper · May 2013
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    ABSTRACT: Various types of biosignals originating from the human body are being extensively used for diagnostics as well as therapeutic interventions. Low-power biological signal processing necessitates energy-efficient filter blocks for time-frequency analysis. In an attempt to reduce the power consumption of an implantable biosignal processor, this paper presents a neuromorphic low-power bandpass filter with excellent figure-of-merit. The charging and discharging profiles of different ionic channels of a Si neuron are utilized to achieve the bandpass filter characteristics. The entire filter structure constitutes 5 transistors working in the weak-inversion saturation regions. Designed in a standard 0.13-μm CMOS process, the proposed bandpass filter consumes only 5 nW with a 0.5 V supply for a center frequency of 200 Hz. The center frequency can be tuned from 150 Hz to 1.5 KHz. The Monte Carlo simulation reveals 58 μVrms input-referred noise and 1% THD for 7 mVp-p of input signal. The proposed architecture also demonstrates excellent figure-of-merit.
    Full-text · Conference Paper · Apr 2013
  • Yang-Guo Li · Mohammad Rafiqul Haider · Yehia Massoud
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    ABSTRACT: This paper presents a low-noise gain-tunable biopotential amplifier that is designed based on a folded-cascode structure. Sub-threshold and self-biasing techniques are employed to achieve a low-noise and low-power amplification. With a bias-current tuning block, the gain of the proposed biopotential amplifier can be precisely adjusted. Designed in a standard 0.13 μm CMOS process, the proposed amplifier provides a 5.9 kHz bandwidth and 30.1 dB gain with 732 nW power. The input-referred noise over the entire bandwidth is 4.3 μVrms , equivalent to a noise-efficiency factor of 2.48.
    No preview · Article · Feb 2013 · Analog Integrated Circuits and Signal Processing
  • Source
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    ABSTRACT: This paper presents a low-power, biologically-inspired silicon neuron based implementation of a chaotic oscillator circuit. The silicon neuron structure is based on Hodgkin–Huxley neuron model. Subthreshold MOSFET and current reuse techniques have been utilized to achieve a low-power consumption of 180.30 nW for the room temperature (27 °C) and typical process corner. The chaotic behavior of the circuit is confirmed by calculating the largest Lyapunov exponent. A sensitivity analysis of the proposed chaotic oscillator shows that the circuit maintains the chaotic behavior for five different process corners within the temperature range of 0–60 °C.
    Full-text · Article · Jan 2013 · Analog Integrated Circuits and Signal Processing
  • S. Smaili · Y. Massoud
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    ABSTRACT: In this paper we propose a reconfigurable receiver that utilizes random demodulation, a compressive sensing architecture for efficient signal projection on a sensing signal. In the proposed system, the sensing signal is designed to annihilate the contribution of undesired frequency components in the collected measurements, thus allowing for the recovery of selected signal bands. The acquisition rate is proportional to the desired signal bandwidth rather than the total bandwidth of the input signal.
    No preview · Conference Paper · Jan 2013
  • S. Smaili · Y. Massoud
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    ABSTRACT: Memristors-based memories utilize the memristor's resistance programmability and small structure to realize high density non-volatile memories. This programmability arises from the dependence of the memristor's resistance on the magnetic flux and total charge, rather than the voltage and current passing through it. However, a critical requirement in memory applications is that the reading scheme should preserve the memristor state after the read. In this paper, we propose a robust reading scheme for memristor-based memories that uses a differential pair sensing amplifier.
    No preview · Conference Paper · Jan 2013

Publication Stats

4k Citations
92.85 Total Impact Points

Institutions

  • 2013-2015
    • Worcester Polytechnic Institute
      • Department of Electrical and Computer Engineering
      Worcester, Massachusetts, United States
  • 2011-2013
    • University of Alabama at Birmingham
      • Department of Electrical and Computer Engineering
      Birmingham, Alabama, United States
  • 2005-2012
    • Rice University
      • Department of Electrical and Computer Engineering
      Houston, Texas, United States
  • 2002-2003
    • Synopsys
      Mountain View, California, United States
  • 1996-2002
    • Massachusetts Institute of Technology
      • • Research Laboratory of Electronics
      • • Department of Electrical Engineering and Computer Science
      Cambridge, Massachusetts, United States
  • 2001
    • Florida State University
      Tallahassee, Florida, United States