[Show abstract][Hide abstract] ABSTRACT: Following the trend of eco-conscious, the automakers tend to use high-voltage packs in the electric vehicle or hybrid electric vehicle. The packs are formed by battery cells in series and parallel connections. Because of the variation of battery production, their capacity, impedance, lifetime and chemistry characteristic vary with ambient temperature. When the batteries are charged or discharged as a pack, the differences result in the imbalance of the battery voltage. The imbalance turns out over-charged and over-discharged and shortens the capacity and lifetime of batteries. Among the equalization methods, resistively switching approach is widely used for its low complexity and low cost. The controller gauges the battery voltage no matter the equalization is on or off. The comparison of two battery voltages must be based on the charging current. If not, the racing phenomenon happens and the equalization circuit would be turned on and off frequently. PWM-based equalization can solve this problem. Detecting the voltages of the batteries when the duty is off ensures the battery voltages are both based on the charging current. The PWM-based equalization successfully eliminates the racing phenomenon and shortens charging time by 48%; from 6200 seconds of switching shunt resistor equalization to 3200 seconds.
[Show abstract][Hide abstract] ABSTRACT: The SOH of batteries is critical information for electric vehicle (EV) and hybrid electric vehicle (HEV) systems. This paper proposes an SOH estimation system based on time-constant-ratio measurement. There are two reasons of choosing time-constant as aging criterion. First, time-constant represents the response speed of terminal voltage during charging and discharging. Second, time-constant represents the change of internal chemical reactions. The proposed estimation resolves the issues of traditional SOH estimations. There are two widely used SOH estimations. The first one is full-charge-capacity (FCC) estimation. Unfortunately, to access FCC information need to take a long-term charging and discharging test. Therefore, FCC estimation fails to be a fast SOH estimation. The second estimation is internal impedance estimation. However, this SOH estimation may cause large error due to the effect of environmental impedance. For improving the above issues on different SOH estimations, this paper proposes an SOH estimation system based on time-constant-ratio measurement. The time-constant-ratio is a novel criterion for aging effect. The use of this novel criterion for SOH estimation helps to achieve the purpose of an environmental-impedance-free and fast SOH estimation. The proposed estimation is 0.14% the measured time of FCC estimation based on 1C charging and discharging. The measured results have average error below 1% and maximum error below 2%.
[Show abstract][Hide abstract] ABSTRACT: Touching devices have become one of the major elements in today's most electronic devices. As the increasing demands of large touching area, the state-of-the-art touching approaches become costly and infeasible. Therefore, it is essential to design a new kind of touch techniques with high touching accuracy and scalability with touching panel size. The purpose of this paper is to provide a touch system that uses the distance between the object (finger or stylus) and its shadow to detect the touch-timing and position. It can be applied to an interactive projection system without using large amount of touch-detecting elements. The proposed touch system only requires a camera and an IR source with an interactive projector to detect the occurrence of touching and its location. The proposed system achieves an average detection rate of 97.53% when the error tolerance is 10 pixels.
[Show abstract][Hide abstract] ABSTRACT: This paper presents a detachable endoscope which is composed of a modified wireless endoscopic capsule and an insertion tube for whole gastrointestinal tract examination. A preliminary In vivo test demonstrates the concept. At present, endoscopes for the whole gastrointestinal
(GI) examination have not been disclosed, they proceed by different types of endoscopes such as esophagoscopy, gastroscopy, and colonscopy which are expensive and nondisposable. In order to overcome these shortcomings, the proposed detachable endoscope here utilizes a conventional endoscope-like
instrument to hold a capsule endoscope at the distal end of insertion tube. In the first step, a control of the movement, the position, and the view angle of the capsule is accomplished by the control section of the detachable endoscope. As the upper digestive tract examination is finished,
the capsule is then released from the insertion tube in the pylorus and switched to wireless mode for small bowel and colon inspection. It is tested with a porcine model, by studying the performance of the detachable endoscope. The discussion on the merits and demerits of this new technology
as a basis for developing a low-cost screening program for whole GI inspection.
[Show abstract][Hide abstract] ABSTRACT: This study investigates image processing using the radial imaging
capsule endoscope (RICE) system. First, an experimental environment is
established in which a simulated object has a shape that is similar to a
cylinder, such that a triaxial platform can be used to push the RICE
into the sample and capture radial images. Then four algorithms (mean
absolute error, mean square error, Pearson correlation coefficient, and
deformation processing) are used to stitch the images together. The
Pearson correlation coefficient method is the most effective algorithm
because it yields the highest peak signal-to-noise ratio, higher than
80.69 compared to the original image. Furthermore, a living animal
experiment is carried out. Finally, the Pearson correlation coefficient
method and vector deformation processing are used to stitch the images
that were captured in the living animal experiment. This method is very
attractive because unlike the other methods, in which two lenses are
required to reconstruct the geometrical image, RICE uses only one lens
and one mirror.
No preview · Article · May 2012 · Optical Engineering
[Show abstract][Hide abstract] ABSTRACT: A varying current charger for rechargeable Lithium-ion battery is implemented to maintain a predefined energy bound which is consumed by the overpotential equivalent resistance. For aged Lithium-ion batteries, the traditional CCCV charging method charges the battery with the same constant current no matter how the battery internal overpotential resistance increases. The varying current charger developed in this paper will follow the pre-defined energy bound, calculate the internal resistance from EMF and update the next charge current by matching the estimated time to consume the energy bound and the end of charge time. The hardware prototype is implemented with a FPGA and a current source board and the communicates with PC user interface through UART. The experiments show that the efficiency for the varying charge current method is hold for both a new battery and an aged battery although the charging time is compromised.
[Show abstract][Hide abstract] ABSTRACT: In the design of capsule endoscope, the trade-offs between battery-life and video-quality is imperative. Typically, the resolution of capsule gastrointestinal (GI) image is limited for the power consumption and bandwidth of RF transmitter. Many fast compression algorithms for reducing computation load; however, they may result in a distortion of the original image, which is not suitable for the use of medical care. This paper presents a novel image compression for capsule gastrointestinal endoscopy, called GICam-II, motivated by the reddish feature of GI image. The reddish feature makes the luminance or sharpness of GI image sensitive to the red component as well as the green component. We focus on a series of mathematical statistics to systematically analyze the color sensitivity in GI images from the RGB color space domain to the two-dimensional discrete-cosine-transform spatial frequency domain. To reduce the compressed image size, GICam-II downsamples the blue component without essential loss of image detail and also subsamples the green component from the Bayer-patterned image. From experimental results, the GICam-II can significantly save the power consumption by 38.5 when compared with previous one and 98.95 when compared with JPEG compression, while the average peak signal-to-noise ratio of luminance (PSNRY) is 40.73dB.
Preview · Article · Jan 2011 · Journal on Advances in Signal Processing
[Show abstract][Hide abstract] ABSTRACT: This paper presents a dual-mode capsule gastrointestinal endoscope device. An endoscope combined with a narrowband image (NBI), has been shown to be a superior diagnostic tool for early stage tissue neoplasms detection. Nevertheless, a wireless capsule endoscope with the narrowband imaging technology has not been presented in the market up to now. The narrowband image acquisition and power dissipation reduction are the main challenges of NBI capsule endoscope. In this paper, we present the first narrowband imaging capsule endoscope that can assist clinical doctors to effectively diagnose early gastrointestinal cancers, profited from our dedicated dual-mode complementary metal-oxide semiconductor (CMOS) sensor. The dedicated dual-mode CMOS sensor can offer white-light and narrowband images. Implementation results show that the proposed 512 × 512 CMOS sensor consumes only 2 mA at a 3-V power supply. The average current of the NBI capsule with an 8-Mb/s RF transmitter is nearly 7 ~ 8 mA that can continuously work for 6 ~ 8 h with two 1.5-V 80-mAh button batteries while the frame rate is 2 fps. Experimental results on backside mucosa of a human tongue and pig's small intestine showed that the wireless NBI capsule endoscope can significantly improve the image quality, compared with a commercial-of-the-shelf capsule endoscope for gastrointestinal tract diagnosis.
No preview · Article · Jan 2011 · IEEE Transactions on Biomedical Circuits and Systems
[Show abstract][Hide abstract] ABSTRACT: This paper presents a memory-efficient motion estimation (ME) technique for high-resolution video compression. The main objective is to reduce the external memory access, especially for limited local memory resource. The key to reduce the memory accesses is based on center-biased algorithm in that the center-biased algorithm performs the motion vector (MV) searching with the minimum search data. While considering the data reusability, the proposed two-step windowing approaches use the secondary windowing as an option per searching necessity. The proposed techniques can save up to 81% of external memory bandwidth and require only 135 MBytes/sec, while the quality degradation is less than 0.2 dB for 720 p HDTV clips coded at 8 Mbits/sec.
[Show abstract][Hide abstract] ABSTRACT: The objective of this paper is to develop an ultra-low-power video compression processor for capsule endoscope to lower the RF transmitter bandwidth. In applications of capsule endoscope, it is imperative to consider battery life and performance trade-offs. Applying state-of-the-art video compression techniques may significantly reduce the image bit rate by their high compression ratio, but they all require intensive computation and consume much power from battery. There are also many fast video compression algorithms for reducing computation load; however, they may result in distortion of original image. A new video compression algorithm for gastrointestinal image based on H.264 Intra-frame encoder and its corresponding VLSI architecture are both proposed for low-power, high bite-rate wireless capsule endoscope. The algorithm exploits the characteristic of gastrointestinal image and H.264 intra-frame prediction technique to reduce computing complexity and save battery power consumption. As the result of implementation, the developed video compressor for 512-by-512 image sensor and 2 Mbits/sec RF transmitter costs 60 k gates and consumes 0.9161 mW power at 2 frames/sec while the average compression rate can be as low as 82%.
[Show abstract][Hide abstract] ABSTRACT: This paper presents a memory-efficient motion estimation (ME) technique for high-resolution video compression. The main objective is to reduce the external memory access, especially for limited local memory resource. The reduction of memory access can successfully save the notorious power consumption. The key to reduce the memory accesses is based on center-biased algorithm in that the center-biased algorithm performs the motion vector (MV) searching with the minimum search data. While considering the data reusability, the proposed dual-search-windowing (DSW) approaches use the secondary windowing as an option per searching necessity. By doing so, the loading of search windows can be alleviated and hence reduce the required external memory bandwidth. The proposed techniques can save up to 81% of external memory bandwidth and require only 135 MBytes/sec, while the quality degradation is less than 0.2dB for 720p HDTV clips coded at 8Mbits/sec.
No preview · Article · Dec 2008 · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
[Show abstract][Hide abstract] ABSTRACT: This paper presents the formal verification method for high-level synthesis (HLS) to detect design errors of dataflow algorithms by using Petri Net (PN) and symbolic-model-verifier (SMV) techniques. Formal verification in high-level design means architecture verification, which is different from functional verification in register transfer level (RTL). Generally, dataflow algorithms need algorithmic transformations to achieve optimal goals and also need design scheduling to allocate processor resources before mapping on a silicon. However, algorithmic transformations and design scheduling are error-prone. In order to detect high-level faults, high-level verification is applied to verify the synthesis results in HLS. Instead of applying Boolean algebra in traditional verification, this paper adopts both Petri Net theory and SMV model checker to verify the correctness of the synthesis results of the high-level dataflow designs. In the proposed hybrid verification method, a high-level design or DUV (design-under-verification) is first transformed into a Petri Net model. Then, Petri Net theory is applied to check the correctness of its algorithmic transformations of HLS, and the SMV model checker is used to verify the correctness of the design scheduling. We presented two approaches to realize the proposed verification method and concluded the best one who outperforms the other in terms of processing speed and resource usage.
No preview · Article · Sep 2008 · International Journal of Software Engineering and Knowledge Engineering
[Show abstract][Hide abstract] ABSTRACT: This paper presents a 14-bit cascaded sigma-delta modulator for broadband telecommunication applications. The modulator is a 2-1-1 cascaded architecture that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.5-MHz signal bandwidth, the modulator achieves a dynamic range of 86 dB and a peak signal-to-noise and distortion ratio of 78.5 dB with an oversampling ratio of 16. The proposed modulator including reference voltage buffers and bandgap circuitry dissipates 62.5 mW from a 2.5-V supply. The active area is 1.2-mm<sup>2</sup> in a 0.25-mum CMOS technology.
No preview · Article · Aug 2008 · Circuits and Systems I: Regular Papers, IEEE Transactions on
[Show abstract][Hide abstract] ABSTRACT: This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μm 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7μm(2) and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply.
[Show abstract][Hide abstract] ABSTRACT: This paper proposes an efficient framework of high-quality image compression method for upper Gastrointestinal tract endoscopy images. The proposed DEWC coding method saves traditional image preprocessing computations, such as demosaicking and color-space transformation, and directly utilizes raw image data acquired from CMOS sensor. R, G and B band image are then separately encoded by wavelet-based SPECK coding. In a cardinal GI tract environment, the spatial frequency distribution of red component is lower than green or blue, and green component is relatively high while compared to blue and red components. DEWC coding saves more bits on red band while allocating more bits on green and blue bands. Therefore, under a fixed compression ratio, such non-uniform bit-rate allocation may earn a better image quality. To measure quality-loss in non-uniform bit-rate allocation, a quality quantified measurement called color-distortion based on CIE94 color-difference formula is also proposed. By using analytical result of color-distortion in bit-rate and bit-rate-difference analysis, an optimal/suboptimal bit-rate allocation scheme can be found by solving linear equations derived from the relationship of color-distortion and bit-rate-difference. When comparing to general JPEG2000 compression standard, the experimental result shows that proposed DEWC coding has a better image quality in color-distortion measurement and more efficient performance in execution time.
[Show abstract][Hide abstract] ABSTRACT: This paper presents a sigma-delta (SigmaDelta) analog-to-digital converter (ADC) for the extended bandwidth asymmetric digital subscriber line application. The core of the ADC is a cascaded 2-1-1 SigmaDelta modulator that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.2-MHz signal bandwidth, the ADC achieves a dynamic range of 86 d 15 and a peak signal-to-noise and distortion ratio of 78 dB with an oversampling ratio of 16. It is implemented in a 0.25-mum CMOS technology, in a 2.8 mm<sup>2</sup> active area including decimation filter and reference voltage buffers, and dissipates 180 mW from a 2.5-V power supply.
No preview · Article · Dec 2007 · IEEE Journal of Solid-State Circuits