Publications (2)0 Total impact
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ABSTRACT: We developed a novel process to achieve ultra-thin gate dielectrics (EOT <0.7 nm) without involving nitrogen incorporation by engineering interface oxide thickness for sub 65nm high-performance logic technology node. Interfacial oxide formation was suppressed by the "oxygen-scavenging effect" using Hf metal on underlying HfO<sub>2</sub> device structure with appropriate annealing. The scavenging Hf metal layer consumes oxygen sources leading to further scaling still using undoped HfO<sub>2</sub>. Using this fabrication approach, EOT of ∼0.9 nm after conventional self-aligned MOSFET process was successfully obtained. In addition, further EOT improvement (EOT: 0.55-0.60nm) was realized in conjunction with nitrogen incorporation using scavenging effect.
Conference Paper: High-k dielectrics and MOSFET characteristics[Show abstract] [Hide abstract]
ABSTRACT: High dielectric constant materials have been investigated for gate dielectric applications. In this paper, various techniques (e.g. optimization of interfacial layer, N and Si incorporation and optimized profiles, forming gas anneal) for improving channel mobility, EOT scaling and reliability of high-k devices is discussed.
University of Texas at Austin
Austin, Texas, United States
- Center for Microelectronics Research