Carbon nanotube thermal interface material for high-brightness light-emitting-diode cooling

Department of Mechanical Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong SAR, People's Republic of China.
Nanotechnology (Impact Factor: 3.82). 05/2008; 19(21):215706. DOI: 10.1088/0957-4484/19/21/215706
Source: PubMed


Aligned carbon nanotube (CNT) arrays were fabricated from a multilayer catalyst configuration by microwave plasma-enhanced chemical vapor deposition (PECVD). The effects of the thickness and annealing of the aluminum layer on the CNT synthesis and thermal performance were investigated. An experimental study of thermal resistance across the CNT array interface using the modified ASTM D5470 standard was conducted. It was demonstrated that the CNT-thermal interface material (CNT-TIM) reduced the thermal interfacial resistance significantly compared with the state-of-art commercial TIM. The optimized thermal resistance of the CNT arrays is as low as 7 mm(2) K W(-1). The light performance of high-brightness light-emitting diode (HB-LED) packages using the aligned CNT-TIM was tested. The results indicated that the light output power was greatly improved with the use of the CNT-TIM. The usage of the CNT-TIM can be also extended to other microelectronics thermal management applications.

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Available from: Philip C. H. Chan, Sep 22, 2015
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    • "This, in order to minimize the electrical contact resistance to the CNT. While many examples are available of growing vertical CNT at moderate to low temperatures using CVD for the fabrication of CNT test vias,[5] [14] [15] [16] [17] [18] [19] [12] or thermal interface materials,[20] [21] none of these examples demonstrates the possibility of growing CNT directly on existing electronic circuits. In this work we integrated CNT, grown using Co on TiN support layers, as vertical interconnects into a monolithic 3D IC process in order to demonstrate the possibility of the direct integration of CNT in IC. "
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    ABSTRACT: Carbon nanotubes (CNT) have been proposed for many applications in integrated circuits (IC): ranging from transistors and interconnects to sensors and actuators. For these applications it is crucial to integrate CNT directly alongside electronics, something which has not been achieved before. In this work we demonstrate the direct growth of CNT alongside CMOS devices, by integrating CNT as vertical interconnect (vias) in a monolithic 3D IC process using techniques and materials compatible with semiconductor technology. The electrical performance of both the CNT vias and the electrical devices is investigated and compared with the literature. From this we can conclude that the CNT growth has no significant impact on the electrical devices, although the resistance of the CNT should be further reduced to compete with metal interconnects. This demonstrates the viability of integrating CNT with IC, which is an important step forward in the application of CNT in electronics.
    Full-text · Article · Jan 2016 · Carbon
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    • "% of the oriented graphene fillers. Previous experiments with aligned fillers used CNTs grown by the chemical vapor deposition (CVD) or by the microwave plasma-enhanced chemical vapor deposition (PECVD) [30] [31] [32] [33] [34] [35] [36] [37]. The approach based on CVD growth requires high temperature processing and complicated assembly. "
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    ABSTRACT: We report on heat conduction properties of thermal interface materials with self-aligning "magnetic grapheme" fillers. Graphene enhanced nano-composites were synthesized by an inexpensive and scalable technique based on liquid-phase exfoliation. Functionalization of graphene and few-layer-graphene flakes with Fe3O4 nanoparticles allowed us to align the fillers in an external magnetic field during dispersion of the thermal paste to the connecting surfaces. The filler alignment results in a strong increase of the apparent thermal conductivity and thermal diffusivity through the layer of nano-composite inserted between two metallic surfaces. The self-aligning "magnetic grapheme" fillers improve heat conduction in composites with both curing and non-curing matrix materials. The thermal conductivity enhancement with the oriented fillers is a factor of two larger than that with the random fillers even at the low ~1 wt. % of graphene loading. The real-life testing with computer chips demonstrated the temperature rise decrease by as much as 10oC with use of the non-curing thermal interface material with ~1 wt. % of the oriented fillers. Our proof-of-concept experiments suggest that the thermal interface materials with functionalized graphene and few-layer-graphene fillers, which can be oriented during the composite application to the surfaces, can lead to a new method of thermal management of advanced electronics.
    Full-text · Article · Aug 2015 · Materials and Design
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    • "Furthermore, the thermal contact resistance of CNT arrays with a copper interface is reported to be only about 10 mm 2 K/W [15]. Simple and efficient methods for growing highly aligned and densely packed CNTs on silicon surfaces were demonstrated in [15]. Horizontal and vertical aligned CNTs were presented in [16]. "
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    ABSTRACT: The increasing power consumption of integrated circuits (ICs) enabled by technology scaling requires more efficient heat dissipation solutions to improve overall chip reliability and reduce hotspots. Rapidly growing 3-D IC technology strengthens the requirement with more devices stacked per unit area. Thermal interface material (TIM) and MicroChannel are widely adopted strategies to resolve the heat dissipation problem. In recent years, carbon nanotubes (CNTs) have been proposed as a promising TIM due to their superior thermal conductivity. Several CNT-based thermal structures for improving chip heat dissipation have been proposed and demonstrated significant temperature reduction. In this project, we developed an improved CNT TIM structure which includes a CNT grid and thermal vias. It collaborates with MicroChannel to dissipate heat more efficiently in 3-D chips and at the same time, obtain more uniform chip thermal profiles. We present simulation-based experimental results that indicate up to 19.88% peak temperature reduction, 7.81% average temperature reduction, over 66% maximum temperature difference reduction on chip and 17.26% improvement in chip reliability for IBM-PLACE 2.0 circuit benchmarks, showing the effectiveness of our proposed thermal structure for resolving thermal challenge and improving chip reliability in 3-D IC.
    Full-text · Article · Apr 2015 · IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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