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Flip chip assembly experiments using small electroplated Au/Sn bumps, i.e. bumps of 50 µm in diameter and less, are carried out. After plating the bumps consist of a Au layer with a thinner Sn layer on top. Normally a reflow process follows. However, the experiments prove that due to geometrical reasons as plated bumps rather than reflowed ones shall be used for bump sizes below 50 µm in diameter in order to achieve a high yield flip chip assembly process. Furthermore thermal cycling tests were carried out using flip chip assemblies consisting of a GaAs die soldered to a BCB thin film Silicon substrate. Most recent results reveal that beside utilizing the self-alignment effect a promising approach to achieve high precision alignment passively is to use micro¬mechanical stops.
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1
Investigation of Solder Bumps, Flip Chip Assembly, Reliability and
Passive Alignment Using Au/Sn
Matthias Hutter, Matthias Klein, Gunter Engelmann, Hermann Oppermann
Fraunhofer IZM, Gustav-Meyer-Allee 25, D-13355 Berlin, Germany, email: hutter@izm.fhg.de
Abstract
Flip chip assembly experiments using small electroplated Au/Sn bumps, i.e. bumps of 50 µm in
diameter and less, are carried out. After plating the bumps consist of a Au layer with a thinner
Sn layer on top. Normally a reflow process in which the bumps are heated up to more than
280 °C follows after which the bumps consist of a thick Au layer with an eutectic solder cap on
top and a ζ-phase layer in between. However, the experiments prove that due to geometrical
reasons as plated bumps rather than reflowed ones shall be used for bump sizes below 50 µm
in diameter in order to achieve a high yield flip chip assembly process. Furthermore thermal
cycling tests were carried out using flip chip assemblies consisting of a GaAs die soldered to a
BCB thin film Silicon substrate. Assemblies with Au/Sn bumps of the size of 30 µm and 50 µm
in diameter were tested this way. Most recent results reveal that beside utilizing the self-
alignment effect a promising approach to achieve high precision alignment passively is to use
micromechanical stops.
Keywords
AuSn Solder, Bumping, Flip Chip, Optoelectronics, Passive Alignment
1. Introduction
Au/Sn solder bumps are especially suited for
flip chip assembly of optoelectronic and RF
devices. Optoelectronic devices have to be
soldered in fluxless processes which can be
applied using Au/Sn solder bumps. The
manufacturing process of RF dice already
includes Au plating which makes the use of
electroplated Au/Sn bumps attractive. The
bumps discussed are manufactured by
electroplating gold and tin in subsequent
process steps. After the plating process the
bumps consist of a thick gold layer and a
thinner Sn layer on top. When the bumps are
heated up to above 280 °C after
electroplating a solder cap forms which
consists of the gold-rich eutectic
microstructure with the composition of
80 wt.-% Au and 20 wt.-% Sn. After this
process step which is called reflow the bumps
consist of a Au layer with an eutectic solder
cap on top (Figure 2). The Au layer which
appears like a pedastal in cross section and
the eutectic solder cap are separated by a
layer of the intermetallic Au5Sn-phase which
is referred to as ζ-phase in the following. The
ratio of gold and tin has to be chosen such
that there is a gold layer left after reflow
below the eutectic cap and the layer of ζ-
phase in order to prevent the liquid eutectic
solder from getting direct contact to the
Ti:W(N) plating base. Assuming direct
contact of solder and Ti:W(N) dewetting
would not necessarily occur. Nonetheless this
metallization is not qualified as a reliable
barrier metal and under bump metallization
2
for eutectic Au80Sn20 solder. This is one
reason why gold is always plated in excess.
Another reason is that the remaining Au acts
as a compliance layer thus enhancing
reliability. During flip chip assembly only the
eutectic part melts while the rest of the bump
remains solid [1, 2, 3].
It has previously been shown that flip chip
assembly with high yield can be performed
using the aforementioned bumping
technology. So it was possible to successfully
develop a flip chip soldering process to join a
large GaAs die which serves as optical switch
with an area of 12*31 mm2 and with more
than 2600 Au/Sn solder bumps in area array
configuration to a ceramic substrate.
Electroplated Au/Sn-bumps of more than
100 µm in diameter have been used for this
application [4]. However, as miniaturization
proceeds bump size and pitch decrease. The
bumps discussed here are 50 µm in diameter
and less. The question arises whether or not
the technology developed for larger bumps
can be transferred to smaller bumps without
any process changes. Therefore, in its first
part this paper is about reflow and flip chip
experiments using miniaturized bumps of a
diameter between 15 µm and 50 µm. The
second part is dealing with reliability of flip
chip joints consisting of GaAs and BCB
thinfilm Si test devices soldered with Au/Sn
solder bumps. The third part describes a new
approach towards passive alignment utilizing
the self alignment effect in combination with
micromechanical stops.
2. Miniaturized Au/Sn Solder Bumps
Reflow and flip chip assembly experiments
were carried out using test devices consisting
of Si test chips and compatible Si test
substrates. These test devices have daisy
chain and four point Kelvin structures in order
to facilitate process development. Figure 1
shows images of test chip and substrate
designed for bumps of 50 µm in diameter at a
pitch of 100 µm. This test vehicle has 4 daisy
chain and 4 four point Kelvin structures.
Furthermore the two daisy chains in the
middle (DC2 and DC3) are designed such
that they can be measured against each other.
In case there is a short between two bumps
which are not in the same daisy chain, a
measurement between the two chains will give
a measurable value for the daisy chain
resistance, otherwise if there is no short
an open circuit will appear.
Figure 1. Photographs of test chip and test
substrate with daisy chain (DC) and four
point Kelvin (FP) structures.
For the experiments the pads on the substrate
wafer were produced by electroplating 3 µm
thick Au. On the chip wafer square shaped
Au/Sn-bumps of 15 µm, 20 µm, 30 µm and
50 µm side length (referred to as diameter in
the following to facilitate matters) were
electroplated. First a 30 µm thick Au layer
was plated before a 6 µm thick Sn layer was
deposited on top of the Au.
After plating had been accomplished some of
the bumps were reflowed by heating the
devices up to more than 280 °C in a liquid
medium and after that SEM pictures of cross
sections were taken. In Figure 2 a bump of
50 µm in diameter after reflow is shown. This
bump has an eutectic solder cap on top of a
3
Au socket and a layer of the ζ-phase in
between. As almost half of the bump volume
is eutectic bumps of such a shape and
composition are regarded as very well suited
for flip chip assembly.
Figure 2. Cross section SEM image of a
Au/Sn bump of 50 µm in diameter after
reflow.
Figure 3. Cross section SEM image of a
Au/Sn bump of 15 µm in diameter after
reflow.
Figure 3 shows the cross section SEM image
of a bump of 15 µm in diameter which reveals
that there is no eutectic left on top of the
bump. Only at the sides eutectic
microstructure can be seen. It is obvious that
bumps with no eutectic on top are not suitable
for flip chip assembly as the ζ-phase stays
solid beyond 500 °C.
The poor results of the reflow experiments
using very small bumps are due to
geometrical reasons: If the solder which forms
during the reflow is too much in volume the
solder will not stay on top of the Au socket
but will wet its side walls. The remelting part
of the bump, i.e. the eutectic solder cap,
encases the remaining Au and thus the usable
cap height decreases (first case in Figure 4).
Although there might be eutectic left on top of
the bump, the amount of eutectic which wets
the side walls of the Au and thus the bump
height is not well controllable. Worst this
could even result in a total phase
transformation of the eutectic part to the ζ-
phase, which melts only beyond 500 °C
(second case in Figure 4). As a consequence,
those bumps would not be flip chip solderable
anymore. The critical cap height is
approximately half of the bump diameter and
should not be exceeded.
Figure 4. If the eutectic cap is larger than
half of the bump diameter the solder which
forms during reflow will not totally stay on
the bump’s top but will wet the side walls of
the gold beneath the solder cap.
For bumps of very small dimensions, i.e. less
than 50 µm in diameter, it is also not possible
4
to simply stay below this critical eutectic
volume because this would not be sufficient
to provide enough solder volume for the
subsequent flip chip assembly process. On
the one hand this is due to the geometrical
reason that a smaller bump diameter
implicates a smaller cap height. On the other
hand this is due the fact that the thickness of
the layer consisting of the ζ-phase is at least
5 µm thick. As thickness of the ζ-phase is
almost independent of bump size it has an
increasing impact with decreasing bump
diameter. Considering a bump of 20 µm in
diameter, the cap height which shall not be
exceeded is 10 µm. As the ζ-phase is at least
5 µm thick, the remaining cap is only 5 µm
high (Figure 5).
Figure 5. Schematic drawing showing the
influence of the bump diameter on the
achievable eutectic solder cap height. As
bump diameter decreases the influence of the
ζ-phase layer increases for its thickness is
approximately 5 µm and is almost
independent of eutectic volume.
In order to prove that flip chip assembly using
50 µm bumps can be performed well but poor
yield is expected using bumps of smaller
dimensions, flip chip assembly tests were
carried out using the aforementioned Si test
devices and reflowed bumps of 15 µm,
20 µm, 30 µm and 50 µm. For each bump
size 3 flip chip assemblies were built by pick-
and-place and reflow in an oven in activated
atmosphere without using flux. After
assembly the electrical resistance of the daisy
chain and four point Kelvin structures was
measured.
Electrical probing of assemblies with 50 µm
bumps revealed only one open daisy chain
circuit so that the yield can be regarded as
good as it was expected.
Figure 6 shows a cross section SEM image of
a 50 µm bump after assembly which was
reflowed prior to assembly. The 3 µm thick
Au layer serving as pad metallization has
totally been dissolved in the molten eutectic
solder. Although the molten eutectic solder
got in direct contact to the Ti:W(N) on the
substrate side no dewetting occurred.
Figure 6. Cross section SEM image of a
bump of 50 µm in diameter after assembly
which was reflowed prior to assembly.
Flip chip assembly of test devices using
bumps of 15 µm and 20 µm in diameter was
not successful. As almost no eutectic was left
on top of the bumps, only very few bumps
soldered to the substrate pads. The
assemblies fell apart during handling
immediately after soldering had been
performed.
5
Assemblies using bumps of 30 µm in
diameter could be built but showed open
circuits, too. Although many bumps are
connected well to the pads as can be seen in
Figure 7 there are bumps which did not wet
the pads at all. In Figure 8 a cross section
SEM image is shown of a bump after
assembly which did not wet the substrate pad
due to the fact that the bump did not provide
enough solder. The Au pad is totally intact.
There was no contact between the pad and the
solder of the bump.
Figure 7. Cross section SEM image of a flip
chip assembly using reflowed bumps of
30 µm in diameter revealing that one bump
did not wet the pad.
Figure 8. Cross section SEM image of a
30 µm bump after assembly which was
reflowed prior to assembly.
The consequence of these findings obviously
is that Au/Sn solder bumps which have a
diameter of much less than 50 µm should not
be reflowed prior to assembly. If the bumps
are used in their as plated condition or aged at
elevated temperature the eutectic composition
is achieved during the soldering process only.
The theory is that the liquid solder cap
forming in the assembly process will get
contact to the metallization of the pads on the
substrate and will wet it rather than wetting
the side walls of the remaining Au on the
bump side. Therefore it should be possible to
achieve good flip chip bonds using Sn layer
thicknesses which in case of applying a
reflow after plating would result in unusable
bumps. Thus, in the next test series flip chip
assembly experiments were carried out using
non reflowed bumps of 30 µm in diameter.
Three assemblies were built using bumps as
plated and another three using bumps which
were aged at 200 °C for 4 hours. Bumps as
plated consist of a Au socket with pure Sn on
top and layers of intermetallic phases in
between as shown in Figure 9. Bumps which
were aged at 200 °C for 4 hours do not show
tin on top any more because it totally
transformed to the intermetallic phases AuSn
and AuSn5 (ζ-phase).
Figure 9. Cross section SEM image of bumps
as plated of 30 µm in diameter.
6
After flip chip assembly measurements of the
electrical resistance of the daisy chain and
four point Kelvin test structures were
performed which proved that all assemblies
were connected with 100% yield, i.e., no open
circuit was found. This is true for assemblies
using as plated bumps as well as bumps that
were aged prior to assembly. Figure 10 shows
the cross section light microscope image of
such a flip chip assembly.
Figure 10. Cross section light microscope
image of a flip chip assembly using bumps of
30 µm in diameter which were aged for
4 hours at 200 °C prior to assembly.
The die shown was aged in air at 200 °C for
4 hours prior to assembly. The results prove
the theory described above that by omitting
the reflow process the geometrical concerns
can be overcome and Au/Sn bumps of small
dimensions are suitable for flip chip
assembly.
3. Thermal Cycling of Flip Chip
Assemblies
For thermal cycling test vehicles designed for
RF measurements and reliability tests with
daisy chain and four point Kelvin structures
as well as RF test structures were used. This
test vehicle comprises a GaAs test chip of an
area of 3.5*3.5 mm2 which is soldered on a
BCB thin film Si test substrate. The
conductors on the Si substrates are made in
microstrip configuration. This means that
there are two metal layers (Cu for ground, Au
for signal) with a BCB layer of 17 µm
thickness in between which forms the
dielectric thin-film. The conductors on the
GaAs die are designed in coplanar
configuration. A photograph of an assembled
test vehicle is given in Figure 11.
Figure 11. Flip chip test vehicle consisting of
a GaAs die on a BCB thinfilm Si substrate.
Complying with the results from the process
development non reflowed Au/Sn bumps
(30 µm Au, 5 µm Sn) were used for flip chip
assembly. Measurements of daisy chain and
four point Kelvin structures showed that flip
chip assembly with almost 100% yield was
achieved. Figure 12 shows a cross section
SEM image of a bump of 30 µm in diameter
after flip chip assembly.
7
Figure 12. Cross section SEM image of a flip
chip interconnection after assembly of test
vehicle.
The Au/Sn-bumps are plated on top of a 3 µm
thick Au layer. As the substrate pads are
made of 6 µm thick Au the molten eutectic
solves Au so that the composition of the
liquid gets Au richer until the composition of
the ζ-phase is reached. As a consequence the
flip chip solder joints consist of Au on the die
side, a region of ζ-phase and a Au layer on
the substrate side. Eutectic microstructure is
not visible any more.
For thermal cycling test vehicles were
assembled using bumps of 30 µm and 50 µm
in diameter. Three types of assemblies were
built, 20 of each, so that 60 samples were
built altogether. Five samples of each type
were underfilled while the remaining 15 of
each type were tested without underfill.
Thermal cycling was conducted over a
temperature range of 55 to 125 °C with 30
min cycles. Electrical probing was done every
25 cycles at the beginning and every 250
cycles at the end of testing. Figure 13 and
Table 1 show the test results.
100 1000
-1,4
-1,2
-1,0
-0,8
-0,6
-0,4
-0,2
0,0
0,2
0,4
0,6
A 30 µm
B 50 µm
C 30 µm
A underfilled
B underfilled
C underfilled
Cumulative Failure logln(1/(1-F))
Cycles
Figure 13. Results of thermal cycling of flip
chip test vehicles.
Non underfilled flip chip assemblies using
bumps of 30 µm in diameter failed
significantly earlier than assemblies using
bumps of 50 µm in diameter. Underfilling the
dice does not result in a significant
enhancement of the characteristic lifetime.
Table 1. Results of thermal cycling. The test
was stopped after reaching 1250 cycles.
Type Number
of
Samples
Bump
Diameter T0 β First
Failur
e
A 13 30 µm 244 2.8 100
B 14 50 µm 1650
2.2 450
C 15 30 µm 397 1.3 100
A underfilled 5 30 µm 647 2.4 350
B underfilled 5 50 µm - - 1250
C underfilled 5 30 µm - - 200
Two different types of assemblies were tested
using bumps of 30 µm in diameter. The
difference between them is that the BCB
passivation opening on the dice of type A was
50 µm while it was 30 µm on dice of type C.
Even though the first failure occurred for both
types after 100 cycles, the characteristic
lifetime differs considerably. The reason for
that is not totally clear.
8
Figure 14. Cross section SEM image of a
solder joint after thermal cycling which
failed between the Ti:W(N) UBM and the Au
socket of the bump. Bump diameter of 50
µm.
Failure analysis showed that the solder joints
of non underfilled assemblies failed at the
interface between the Au socket of the bump
and the Ti:W(N) sputter layer. Figure 14
shows a SEM image of a cross section of a
solder joint of a non underfilled sample after
it failed in thermal cycling. The diameter of
the bump is 50 µm. The failure is located at
the interface between the bump and the
sputtered Ti:W(N) plating base.
In addition to the analysis of cross sections
pull tests of cycled non underfilled test
vehicles were performed. Figure 15 shows a
SEM image of a pulled test die with view on
the failed interface. It is proved that the
failure occurred between the Ti:W(N) and the
Au socket of the bump as the Ti:W(N) plating
base remained on the GaAs die. This means
that the interface between the sputtered
Ti:W(N) metallization and the electroplated
Au is the weakest interface. As this bump did
not fail to 100% in the center of the image
there is Au visible which stems from the Au
pedastal of the bump. It was found that the
failure mode which was identified by
analyzing non underfilled samples is the same
for early failures and for late failures.
Figure 15. SEM image of GaAs test die after
thermal cycling and pull test. View on the
pulled GaAs die (type A die).
Figure 16. Cross section SEM image of an
underfilled sample that failed due to a crack
which started between chip and underfill at
the upper edge of the chip, propagated
between underfill and chip and crossed the
underfill, the conductor line and the BCB
beneath the Au.
9
Underfilled samples did not fail at the flip
chip solder joints but the failure is due to a
crack of the Au conductor line on the Silicon
BCB thin film substrate. In Figure 16 it can be
seen that the crack starts at the upper edge of
the die and propagates along the interface
between die and underfill material, crosses
the underfill and the Au conductor which
causes the electrical failure.
After crossing the Au conductor the crack
propagates into the BCB layer and stops at
the interface of BCB and Si as can be seen in
Figure 17.
Non underfilled as well as underfilled
samples never failed in the Au/Sn solder
joints but either between the UBM and Au in
non underfilled samples or due to a lack of
underfill adhesion to the GaAs die in
underfilled samples.
Figure 17. Fracture of Au conductor in
detail. The crack propagated further and
caused a delamination at the BCB-silicon
interface, too.
4. Passive Alignment
In optoelectronics packaging there is an urgent
need for cost reduction. Therefore it is
desirable to realize packaging solutions which
make passive alignment possible. A
promising approach towards passive
alignment is utilizing the self alignment effect
during flip chip soldering, which has already
been investigated using AuSn solder bumps
[3], in combination with the implementation of
micro-mechanical stops on chip and substrate.
In order to show that this approach is viable,
Si test devices with stops were designed and
fabricated by Reactive Ion Etching. On the
chip wafer AuSn solder was deposited by
electroplating and reflow. On the substrate
wafers Ni/Au pads were deposited. After
plating AuSn and Ni the wafers were diced. A
SEM image of a test vehicle Si chip is shown
in Figure 18.
Figure 18. Test vehicle for evaluation of
passive alignment. Chip with stops and
electroplated AuSn solder bumps.
10
Figure 19. Cross section of a flip chip
assembly. Passive alignment is achieved by
using etched mechanical stops on chip and
substrate side.
Flip chip assembly tests were conducted by
means of pick & place and reflow in an oven
in a fluxless soldering process. Most recent
results prove that it is possible to achieve
passive alignment at least in two directions in
space even though the yield has to be
improved.
Figure 20. Cross section SEM image. The
micro-mechanical stops are in direct contact
to each other.
A cross section light microscope image of a
flip chip assembly is shown in Figure 19. The
movement of the chip in regard to the
substrate is interrupted as soon as the
mechanical stops have reached each other.
Figure 20 shows a SEM micrograph of a cross
section through the stops which are in direct
contact to each other. This means the passive
alignment has been achieved in two
directions.
Conclusions
Reflow and flip chip assembly tests using
electroplated Au/Sn bumps of between 15 µm
and 50 µm in diameter were carried out.
Bumps of 15 µm, 20 µm and 30 µm in
diameter may not be reflowed prior to
assembly otherwise they are unusable. This is
due to geometrical reasons which are
overcome by using non reflowed bumps. Flip
chip assembly using non reflowed bumps
resulted in almost 100% yield.
Flip chip test vehicles consisting of GaAs
dice and BCB thin film Si substrates were
produced using non reflowed bumps of 30 µm
and 50 µm in diameter. Thermal cycling was
performed. The failure mode could be
identified as fracture between the Au of the
bump and the Ti:W(N) plating base in
assemblies which had not been underfilled.
Underfilled assemblies did not fail at the flip
chip interconnections but due to a fracture in
the Au conductors on the BCB thinfilm Si
substrate.
Most recent results regarding passive
alignment have been presented. Using Si test
vehicles it could be shown that passive
alignment is possible. Future work shall be
focused on developing a robust flip chip
process.
References
1. Dietrich, L., Engelmann, G., Ehrmann, O.,
Reichl, H., “Gold and Gold-Tin Wafer
Bumping by Electrochemical Deposition
for Flip Chip and TAB,” 3rd European
11
Conference on Electronic Packaging
Technology (EuPac’98), Nuremberg,
Germany, June 15-17, 1998.
2. Kallmayer, C., Lin, D., Kloeser, J.,
Oppermann, H., Zakel, E., Reichl, H.,
“Fluxless Flip-Chip Attachment
Techniques Using the Au/Sn Metallurgy,”
17th International Electronics
Manufacturing Symposium, IEMT’95,
Austin, Texas, 1995.
3. Kallmayer, C., Oppermann, H., Kloeser, J.,
Zakel, E., Reichl, H., “Experimental
Results on the Self-Alignment Process
Using Au/Sn Metallurgy and on the
Growth of the ζPhase During the
Reflow,” Proc. International Flip Chip,
Ball Grid Array, TAB and Advanced
Packaging Symposium, ITAP’95, San Jose,
1995.
4. Hutter, M., Oppermann, H., Engelmann,
G., Wolf, J., Ehrmann, O., Aschenbrenner,
R., Reichl, H., “Calculation of Shape and
Experimental Creation of AuSn Solder
Bumps for Flip Chip Applications,” Proc
52nd Electronic Components and
Technology Conf, San Diego, 2002.
ResearchGate has not been able to resolve any citations for this publication.
Conference Paper
Eutectic Au/Sn 80/20 solder is used more and more for flip chip assembly especially of optoelectronic devices because no flux is necessary during soldering. Galvanic deposited AuSn bumps are created on wafer scale and therefore are of interest in terms of costs. The creation of electroplated AuSn bumps comprises the galvanic deposition of Au and Sn in successive steps followed by a reflow in liquid medium which is necessary to form the eutectic solder cap on top of the bumps. Depending on the application the pitch and the height, diameter and shape of the bumps have to be chosen. The shape of the bump (i.e. the height of the total bump and the thickness of the eutectic cap as well as the height of the remaining Au socket beneath the eutectic solder cap) can be adjusted by calculating the heights of the Au and Sn layers that are deposited. The remaining Au socket absorbs emerging stresses during soldering and during thermal cycling. The bumps' shape is calculated prior to the experimental setup. The bumps are created experimentally by means of electroplating and reflow in liquid medium and are analyzed using cross sections and SEM. Different bump diameters and thicknesses of the Sn cap are used. The microstructure of the eutectic solder cap, the shape of both the solder cap and the remaining Au socket as well as the formation of intermetallic phases are investigated and discussed.
Conference Paper
With the use of the Au/Sn system as solder metallurgy different fluxless flip-chip processes are possible. In the studies for this paper Au/Sn bumped chips are used for soldering in an infrared oven under activated atmosphere with the self-alignment mechanism. A new approach is the successful application of the Au/Sn metallurgy for vapor phase soldering which provides the self-alignment effect as well. Flip-chip bonding on rigid and flexible substrates using a pulse heated thermode is also demonstrated. The scope of this paper is to show the development of different fluxless flip-chip processes with Au/Sn metallurgy on thin film and thick film substrates. The wetting of the pads, the fillet formation and the growth of ζ-phase are the major subjects of the studies as they determine the bonding result. Shear tests were performed in order to quantify the quality of the interconnection. The results obtained by the different methods are compared and conclusions about the investigated processes drawn
Gold and Gold-Tin Wafer Bumping by Electrochemical Deposition for Flip Chip and TAB
  • L Dietrich
  • G Engelmann
  • O Ehrmann
  • H Reichl
Dietrich, L., Engelmann, G., Ehrmann, O., Reichl, H., "Gold and Gold-Tin Wafer Bumping by Electrochemical Deposition for Flip Chip and TAB," 3rd European Conference on Electronic Packaging Technology (EuPac'98), Nuremberg, Germany, June 15-17, 1998.
Experimental Results on the Self-Alignment Process Using Au/Sn Metallurgy and on the Growth of the ζ-Phase During the Reflow
  • C Kallmayer
  • H Oppermann
  • J Kloeser
  • E Zakel
  • H Reichl
Kallmayer, C., Oppermann, H., Kloeser, J., Zakel, E., Reichl, H., "Experimental Results on the Self-Alignment Process Using Au/Sn Metallurgy and on the Growth of the ζ-Phase During the Reflow," Proc. International Flip Chip, Ball Grid Array, TAB and Advanced Packaging Symposium, ITAP'95, San Jose, 1995.