Effects of Through-BOX vias on SOI MOSFETs

Conference Paper · May 2008with12 Reads
DOI: 10.1109/VTSA.2008.4530815 · Source: IEEE Xplore
Conference: VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on

    Abstract

    The metal-filled vias through the buried oxide are integrated with silicon-on-insulator (SOI) MOSFETs. The FET temperature, measured directly using integrated junction diodes, can be lowered by as much as 25degC with these vias. In addition to enhanced DC characteristics, lowered gate resistance and output conductance further improve the RF performance and the extent of improvement is dependent on the FET design.