Conference Paper

Comparison of output drivers for high-speed serial links

Fac. of Eng., Ain Shams Univ., Cairo
DOI: 10.1109/ICM.2007.4497722 Conference: Microelectronics, 2007. ICM 2007. Internatonal Conference on
Source: IEEE Xplore


A comparison between the performance of a current-mode differential signaling driver and a voltage mode driver for high-speed (HS) serial links is presented. Minimum power consumption, minimum area, minimum added jitter, and maximum immunity to power supply noise are the main figures of merit. Both drivers employ on-chip termination to eliminate reflections and pre-emphasis to reduce inter-symbol-interference (ISI) in order to enhance signal integrity and operating speed. They are implemented in 0.13 mum CMOS process using 1.2-V power supply. Both drivers support multiple output voltages and pre-emphasis ratios.

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    • "A current-mode differential driver has been more popular than a voltage-mode differential driver in a highspeed serial link for its immunity to power supply noise and ease of impedance matching [1]. For the same voltage swing, the power consumption of a current-mode driver, however, is larger than that of a voltage-mode driver and therefore a voltage-mode driver is drawing lots of interest especially for low-power serial link [2] [3]. "
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    ABSTRACT: A 6-Gb/s differential voltage mode driver is presented whose output impedance and pre-emphasis level can be controlled independently. The voltage mode driver consists of five binary-weighted slices each of which has four sub-drivers. The output impedance is controlled by the number of enabled slices while the pre-emphasis level is determined by how many sub-drivers in the enabled slices are driven by post-cursor input. A prototype transmitter with a voltage-mode driver implemented in a 65-nm CMOS logic process consumes 34.8-mW from a 1.2-V power supply and its pre-emphasized output signal shows 165-mVpp,diff and 0.56-UI eye opening at the end of a cable with 10-dB loss at 3-GHz.
    Preview · Article · Oct 2013 · Journal of Semiconductor Technology and Science
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    • "In this context, the use of SOI technology can greatly enhance the performance of the SERDES output driver due to the inherently reduced junction capacitance [5]. The current-mode driver described in [6] is implemented in this work using 0.13 µm Bulk CMOS and Partially-Depleted (PD) SOI technologies provided by the same foundry. "
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    ABSTRACT: A current-mode output driver that supports SERDES applications is implemented using 0.13 mum Bulk and PD SOI CMOS technologies. Schematic simulation results confirm the enhanced performance of PD SOI for very high-speed interfaces. The PD SOI current-mode driver shows a 3 times lower data dependent jitter than the bulk current-mode driver at the same 3.125 Gbps data rate of XAUI standard.
    Full-text · Conference Paper · Nov 2009
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    ABSTRACT: This paper describes a low power two-tap voltage-mode transmitter (Tx) in 45 nm CMOS process technology with adaptive de-emphasis and impedance self-calibration in which the adaptive de-emphasis is independent of the impedance self-calibration. The Tx comprises of eight identical slice units where the impedance of each slice unit is controlled by impedance calibration circuit to match the characteristic impedance of the transmission line. Voltage-mode (VM) driver can save 75 % static output power compared to current-mode (CM) driver. The proposed design provides a differential output swing of 800 mV-1200 mV across process, voltage and temperature (PVT) variation with a power consumption of 10 mW at a data rate of 5 Gb/s under a supply voltage of 1 V. The eye of the received data has 0.9 unit interval (UI) timing margin when the data signals are sent over 20" FR4 channel.
    No preview · Conference Paper · Jun 2012
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