Conference Paper

A fully static scheduling approach for fast cycle accurate SystemC simulation of MPSoCs

LIP6/UPMC, Univ. Pierre et Marie Curie, Paris
DOI: 10.1109/ICM.2007.4497671 Conference: Microelectronics, 2007. ICM 2007. Internatonal Conference on
Source: IEEE Xplore


This paper presents principles and tools to facilitate multi-processor system on chips (MPSoCs) design and modeling, and to speed up cycle accurate SystemC simulation. We describe an effective way to build an hardware architecture virtual prototype, using a library of SystemC simulation models based on communicating synchronous finite state machines. This modeling approach supports a fully static scheduling strategy, based on the analysis of the combinational dependency graph. Our static scheduling algorithm has been implemented in the SystemCASS simulator, and provides speed-up of one order of magnitude versus the standard event-driven SystemC simulation engine. The modeling approach proposed in this paper has been adopted by the SoCLIB French National Project, that is an open modeling and simulation platform for multi-processors system on chips.

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Available from: Richard Buchmann, Jan 19, 2015
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    • "More abstract estimation techniques are required to enable early design decisions. To achieve this goal, several studies have proposed evaluating power consumption at higher abstraction levels such as the CABA level [1] [12], on which this work is based. At this level, the behavior of components is simulated cycle by cycle using an architectural level simulator. "
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    ABSTRACT: Copyright © 2011 Chiraz Trabelsi et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. As technology scales for increased circuit density and performance, the management of power consumption in system-on-chip (SoC) is becoming critical. Today, having the appropriate electronic system level (ESL) tools for power estimation in the design flow is mandatory. The main challenge for the design of such dedicated tools is to achieve a better tradeoff between accuracy and speed. This paper presents a consumption estimation approach allowing taking the consumption criterion into account early in the design flow during the system cosimulation. The originality of this approach is that it allows the power estimation for both white-box intellectual properties (IPs) using annotated power models and black-box IPs using standalone power estimators. In order to obtain accurate power estimates, our simulations were performed at the cycle-accurate bit-accurate (CABA) level, using SystemC. To make our approach fast and not tedious for users, the simulated architectures, including standalone power estimators, were generated automatically using a model driven engineering (MDE) approach. Both annotated power models and standalone power estimators can be used together to estimate the consumption of the same architecture, which makes them complementary. The simulation
    Full-text · Article · Apr 2011 · EURASIP Journal on Embedded Systems
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    ABSTRACT: Nowadays, single-chip cache-coherent multi-cores up to 100 cores are a reality. Many-cores of hundreds of cores are planned in the near future. Due to the large number of cores and for power efficiency reasons (performance per watt), cores become simpler with small caches. To get efficient use of parallelism offered by these architec-tures, applications must be multi-threads. The POSIX Threads (PThreads) standard is the most portable way to use threads across operating systems. It is also used as a low-level layer to support other portable, shared-memory, parallel environments like OpenMP. In this pa-per, we propose to verify experimentally the scalabil-ity of shared-memory, PThreads based, applications, on Cycle-Accurate-Bit-Accurate (CABA) simulated, 512-cores. Using two unmodified highly multi-threads ap-plications, SPLASH-2 FFT, and EPFilter (medical im-ages noise-filtering application provided by Phillips) our study shows a scalability limitation beyond 64 cores for FFT and 256 cores for EPFilter. Based on hardware events counters, our analysis shows: (i) the detected scal-ability limitation is a conceptual problem related to the notion of thread and process; and (ii) the small per-core caches found in many-cores exacerbates the problem. Finally, we present our solution in principle and future work.
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