Conference Paper

Low power sigma delta modulator with dynamic biasing for audio applications

Tamkang Univ., Taipei
DOI: 10.1109/MWSCAS.2007.4488561 Conference: Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on
Source: IEEE Xplore


In this paper, a low power sigma delta modulator with dynamic biasing technique is presented. According to the analysis of the operations of the switched-capacitor integrator, the folded-cascode operational amplifier can be designed with optimized biasing currents in three different phases to reduce power dissipations. The total power saving is 20% of the general one. A prototyping fourth order single-bit MASH 2-2 sigma delta modulator is designed with the technique of dynamic biasing to achieve dynamic range of 95 dB and peak signal-to-noise-and-distortion-ratio of 93 dB. The experimental circuit is designed in 0.35 mum 2P4M CMOS technology. The chip area is 3.11 mm2, and the power dissipation is only 5 mW from a supply voltage of 3 V.

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    • "Several techniques have been used to achieve high resolution and low power operation in Sigma-Delta modulators. With the objective of achieving low power consumption, it is presented in [1] a Sigma-Delta modulators in which the bias current of the amplifier is adjusted in accordance with the phase of operation, namely sampling, slewing and settling, thus reducing the overall current consumption. In [2] the modulator uses a low-distortion feed-forward topology with non-linear local feedback, to enhance the linearity and reduce power. "
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    ABSTRACT: Analog-to-digital converters provide a vital interface in mixed-signal electronic systems. One of the typical approaches to implement high-resolution sigma-delta modulators often involves the choice of high-order loop-filters, which imply the use of a large number of integrators. As in common topologies each integrator is implemented by one operational amplifier, high-order modulators can demand a high number of operational amplifiers, increasing the total circuit area and power consumption. In order to overcome this feature, a shared-opamp technique is explored in this work. It is a 4 th -order sigma-delta modulator, with the first stage being implemented by one op-amp, and the last 3 stages being shared by the same op-amp. This fact makes possible not only to reduce the total power consumption of the integrators, but also reduces the total number of op-amps by half, which lead to area reduction. Simulations results show a peak SNR of 100.1 dB and a THD of -80 dB were achieved for the audio band from 20 to 20 kHz, with a total power consumption of 9.83 mW, using the X- FAB 1.8 V CMOS 0.18 technology.
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    ABSTRACT: This paper presents a high-speed CMOS OP Amp with a dynamic switching bias circuit capable of processing video signals of over 2 MHz with slight nonlinearity and low dissipated power. The OP Amp, capable of operating at 10 MHz dynamic switching rate, was designed and showed through simulations a dissipated power of 60% of that in conventional continuous operation. A switched capacitor (SC) non-inverting amplifier with a gain of 2 employing this OP Amp and its high-speed 10 MHz dynamic switching operation, capable of processing video signals, was demonstrated. By increasing the switching duty ratio to 70%, its power dissipation decreased to 62% of that in normal operation. The output voltage inaccuracy for a SC amplifier with a gain of below 2 was below 1 % and mainly caused by the static nonlinearity of the OP Amp. This circuit configuration should be very useful in realizing low-power wide-band signal processing ICs.
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