Conference Paper

Analog Design Considerations For Independently Driven Double Gate MOSfets And Their Application in a Low-Voltage OTA

CEA Leti-MINATEC, Grenoble
DOI: 10.1109/ICECS.2007.4510964 Conference: Electronics, Circuits and Systems, 2007. ICECS 2007. 14th IEEE International Conference on
Source: IEEE Xplore


This paper explores new capabilities brought on by Independently Driven Double Gate CMOS transistors (IDGMOS) for analog baseband design. Since the gates are disconnected, the corresponding channels are coupled resulting in a dynamic threshold voltage tuning. This operation mode is exploited to create new analog functions and low-voltage circuits. A current mirror is redesigned using IDGMOS and it is shown that this structure performs an efficient differential function relating to the potentials applied to the back gates. Being adapted to low-voltage operation and self compensated from input common-mode variations, the differential current mirror is employed for the active loading of a low-voltage fully-balanced OTA. It then improves the limited common-mode rejection of the original OTA structure by providing output feed-back and input feed-forward compensation.

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    • "The usefulness of non-classical underlap channel architecture to enhance both gain and bandwidth of an OTA, alleviating gain-bandwidth trade-off associated with analog design, has been demonstrated in [8]. A. Kumar et al, [9] explores the application of independently driven double-gate MOSFETs for low-power low voltage analog integrated circuit design. In [10], P.Freitas et al, investigate new capabilities brought on by independently driven double gate CMOS transistors for analog baseband design. Since the gates are disconnected, the corresponding channels are coupled resulting in a dynamic threshold voltage tuning. "
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    ABSTRACT: Recently, multi-gate MOSFETs such as double-gate MOSFETs have been identified as inevitable inclusion for future nano-scale circuit design. This paper explores the scope of tied-gate (3T), independent gate (4T), symmetric and asymmetric features of double-gate MOSFETs (DGMOSFETs) for ultra-low power and high efficient rectifiers for RFID applications. Various widely used rectifier topologies such as simple conventional rectifier, self-Vth cancellation (SVC) rectifier and differential drive rectifier etc, have been designed to investigate the better candidate for DGMOSFET technology. Analysis reveals that 3T differential drive rectifier topology shows the maximum power conversion efficiency (PCE) and higher DC output voltage level generation. Second part of the work further explores the effects of 3T/4T and symmetric/asymmetric features of DGMOSFETs on the performance of differential drive rectifier. Among the various DGMOSFET configurations for RFID rectifiers, symmetric tied-gate DGMOSFETs have the best power conversion efficiency and the lowest power consumption.
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    ABSTRACT: Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low I<sub>OFF</sub> (< 20 pA/mum) and high I<sub>ON</sub> (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer from discrete width layout constraints and can benefit from specific options like independent gate operation.
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    ABSTRACT: This paper describes an explicit compact model of an independent double gate (IDG) MOSFET with an undoped channel. This model includes short channel effects and also mobility reduction, saturation velocity, series resistance and a charge model. It is applicable for symmetrical, asymmetrical and independent gate devices. The validity of this model is demonstrated by comparisons with ATLAS two-dimensional numerical simulations.
    Preview · Article · May 2009 · Solid-State Electronics
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