The aggressive downward scaling of silicon technology node has resulted in rapid shrinking of both front-end and back-end devices over the past decade [1]. This has led to a surge in on-chip current density, approaching or exceeding the current-carrying capacity of the present industry-standard interconnect material Cu, ~1MA/cm 2 [2]. In order to keep up with this increase in current density, new
... [Show full abstract] materials with higher current capacity than Cu and comparable or lower interconnect resistance are being investigated. Nanocarbons such as carbon nanotubes (CNTs) and graphene are strong candidates owing to their high current capacities and near-ballistic transport. In particular, vertically aligned CNTs grown on a metal underlayer are especially promising as the replacement for Cu in interconnect vias, as they can be engineered to yield via resistance comparable to that of Cu and can withstand much higher current [3]. Such resistance comparison for the targeted 30 nm-diameter vias is given in Table I. To study the electrical and structural properties of CNT vias, test structures with varying via diameters ranging from 0.5 μm to 1.0 μm were fabricated and patterned on a SiO 2 /Si substrate [4]. The via height is 1.0 μm for all diameters and the metal underlayer is Pt. Figure 1(a) shows a cross-sectional schematic of the test structure and Figure 1(b) displays an SEM image of an array of patterned vias. After patterning the vias, Ni is electrodeposited on the base of each via using nickel sulphamate, nickel chloride, and boric acid in an aqueous bath [5]. The cross-sectional view of a typical via after Ni electrodeposition is shown in Figure 1(c). The test chip is baked in high vacuum for 2 hours to drive away the S and Cl contents in the electrodeposited Ni film. It is subsequently placed in a plasma-enhanced chemical vapor deposition (PECVD) system and heated up to 650 C to dewet the deposited Ni film before a reducing gas, NH 3 , and carbon source, C 2 H 2 , are introduced into the reaction chamber. The plasma is then generated using an applied voltage of 800 V, which aids in dissociating the hydrocarbon, with the resulting carbon precipitated on the dewetted Ni catalyst. The applied field is also instrumental in the vertically-aligned growth of carbon nanotubes. Figure 2(a) shows an SEM image of a 1.0 μm via after CNT growth and Figure 2(b) shows a high-resolution image of a 0.5 μm via used for electrical measurements. After growth, the CNT array in each via is subjected to a preliminary resistance test and subsequent current stressing up to 500 μA, which serves to reduce probe-to-CNT array contact resistance by two to three orders of magnitude [6]. Current-voltage measurements are then carried out on each via, and the result for a 0.5 μm via is given in Figure 3. Detailed electrical characterization of the test devices along with images of the CNT-metal underlayer metal interface will be obtained, and measurements on CNT vias filled with a dielectric material and with a top metal pad will also be presented.