A Top-Down Design Verification Based on Reuse Modular and Parametric Behavioral Modeling for Subranging Pipelined Analog-to-Digital Converter
This paper proposes a new approach to high speed pipelined A/D converter design. This technique combines a known subranging technique into pipelined architecture. A 8-bit 100 MSample/s subranging pipelined analog-to-digital converter (ADC) is implemented using this technique. The calibration techniques used are namely digital error correction, redundancy, and coarse and fine synchronization. To validate the proposed ADC, a top-down design methodology based on modular and parametric behavioral components is adopted. It supports a design process where non-ideal effects are incorporated in an incremental way, allowing easy architectural selection with fast and accurate simulations. The behavioral models are written in standard hardware description language, Verilog-AMS.
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