Conference Paper

Design Methodology of Low Power JPEG2000 Codec Exploiting Dual Voltage Scaling

Dept. of Electron. Eng., Tsinghua Univ., Beijing
DOI: 10.1109/ICASIC.2005.1611280 Conference: ASIC, 2005. ASICON 2005. 6th International Conference On, Volume: 1
Source: IEEE Xplore


This paper proposed a novel dual voltage scaling layout architecture and a design methodology of low power JPEG2000 codec exploiting dual voltage scaling. Fabricated in SMIC 0.18mum 1P6M standard CMOS technology, this codec is capable of JPEG2000 compression/decompression with a 1280times1024 pixel (YUV422 full color) at 20 frames/s employing 100MHz operation frequency. And the power consumption is 465mW @ 1.8V and 100MH. Applied with dual voltage scaling technique, the power dissipation is reduced by 28.5%

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Available from: Li Zhang, Nov 12, 2015
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    ABSTRACT: With the evolution of the GSM mobile to a multi-media mobile terminal, optimizing the power consumption becomes an extremely complex task. New operating modes like the MP3 player mode or high resolution graphic games gain significant importance from a power consumption point-of-view. Submicron technologies with their significantly increased leakage currents pose another new challenge. New power concepts are required to achieve reasonable operating and standby times. The design methodology, power estimation and optimization of low power have to be pursued at all stages of the design down to gate level. They also have to be compatible with standard or custom software to minimize the impact on time-to-market for the custom product. This paper mainly talks about the lower power techniques implemented at system/architecture and register transfer level in a complex mix-signal mobile baseband SoC, low-power design optimization flow, power management technique fulfilling mobile application and on-chip low-power memory.
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