Integration of Cu and extra low-k dielectric (k=2.5∼2.2) for 65/45/32nm generations

Conference PaperinElectron Devices Meeting, 1988. IEDM '88. Technical Digest., International 2005:4 pp.- · January 2006with21 Reads
DOI: 10.1109/IEDM.2005.1609273 · Source: IEEE Xplore
Conference: Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
This paper investigated various approaches to integrate Cu and extra low-k dielectric (ELK, k=2.5∼2.2) for dual damascene fabrication. We demonstrate a trench-first hard mask process flow without k degradation by ash-free process and a novel pore sealing technique. In addition, we have extended this pore sealing concept to a via-first PR mask approach for porous ELK of 2.2. Both optimized hard mask and PR mask process flows are demonstrated promising for Cu/ELK integration for 65/45/32nm generations.
  • [Show abstract] [Hide abstract] ABSTRACT: For the first time, this paper presents the results of successful integrations of Cu wiring into a production 512 Mb/90 nm design-rule stacked capacitor and recessed gate DDR (double data rate) DRAM technology, focusing on the effects of Cu integration on DRAM performance, yield, refresh time, and wafer-level reliability. 2 levels Cu interconnect (Ml single damascene and M2 dual damascene) and CVD low-k (FSG) materials have been implemented. Both the reduction in parasitic capacitance and line resistance were found to improve the operation speed of DRAM. No degradation was observed in view of normalized refresh time and yield with Cu wiring. The reliability issues with Cu integration to DRAM were systematically evaluated. In conclusion, this study demonstrates that the Cu wiring is fully compatible with the conventional DRAM and will be expected to meet the requirements of high-performance and high-speed advanced DRAM beyond sub-50 nm node.
    Conference Paper · Jul 2007