A VLSI GFP frame delineation circuit
Inst. of Commun. & Inf. Technol., Queen Univ., Belfast, UKDOI: 10.1109/ISVLSI.2006.14 Conference: Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on, Volume: 00
Source: IEEE Xplore
This paper presents the design and study of circuit architecture able to perform 16 Gbps GFP frame delineation with single bit error correction using UMC 130 nm standard cell technology. The design targets the development of a hard macro core for the design of next generation network processing platforms.
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