Conference Paper

ESD-induced internal core device failure: New failure modes in System-on-Chip (SOC) designs

Global Technol. Leader, Santa Clara, CA, USA
DOI: 10.1109/IWSOC.2005.58 Conference: System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on
Source: IEEE Xplore


With MOSFET scaling, increased design complexity, and multiple system power domains, ESD failures occur in internal core areas which are not connected to external package pins. A review of the various internal core device failure mechanisms and design recommendations are presented.

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    • "Introducing a valid-criterion and a fail-voltage together with the basic circuit elements in the models it is possible to use every circuit simulator for the calculations. 3.3 Possible hot spots in the core Possible victims for damage are interface devices between two or more voltage domains (Huh, 2005). In figure 2 a simplified product example is drawn with interfaces between different supply blocks. "
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