Design and test methodology for a reconfigurable PEM data acquisition electronics system
ProsysLab/INESC-ID, Lisbon, Portugal
DOI: 10.1109/FPL.2005.1515776 Conference: Field Programmable Logic and Applications, 2005. International Conference on
The purpose of this paper is to present the main aspects of a design and test (D&T) methodology used in the development of a specific type of system. The application focuses medical imaging using a compact positron emission mammography (PEM) detector with 12288 channels, targeting high selectivity and spatial resolution. The system operates at 100 MHz, with a data acquisition rate of 1 million events per second, under a total single photon background rate in the detector of 10 MHz. In this paper, the data acquisition electronics (DAE) system of the clear-PEM detector is used as vehicle for demonstrating the characteristics and versatility of the D&T methodology. For production and lifetime test, robust functional-oriented built-in self test (BIST) structures are developed. A design challenge in this context is the need to identify relevant data out of a huge amount of data streams. Another design challenge is the need to guaranty synchronism, without which data would become meaningless. Hierarchy, modularity, parallelism and pipelining are extensively exploited to meet these stringent system requirements. DAE implementation involves eight 4-million, one 2-million and one 1-million gate FPGAs (Xilinx Virtex II).
Available from: Pedro Lousã
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ABSTRACT: The purpose of this paper is to describe key aspects of the integration and test of the Data Acquisition Electronics (DAE) in the PEM (Positron Emission Mammography) system. The main aspects highlighted are the methodology and strategies followed to test and validate the functionality and performance of the complete physical system. Test procedures are also described. These tests are controlled by the different FPGAs (Field Programmable Gate Array) that implement the DAE system functionality. Results of test and validation on FPGAs, boards and buses are presented.
Available from: J.P. Teixeira
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ABSTRACT: The purpose of this paper is to present a new robust methodology for synchronous communications in a BUS, connecting multi-clock domains. Traditionally, when robust solutions are needed, an asynchronous communication is used. However, the low transfer rates associated with asynchronous solutions make them inadequate for high performance digital systems. On the other hand, synchronous communications do not guarantee dependability for all data, especially when different clock domains are interconnected. In this paper we propose to take advantage of these approaches, by combining, the robustness of asynchronous communication and the speed and simplicity of synchronous communications. A structure has been developed to implement the proposed communication approach. A test chip has been designed to implement that structure and prove the concept. The usefulness of the methodology is demonstrated in a complex FPGA data acquisition system. Simulation results are presented.
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