Conference Paper

Issues and optimization of millisecond anneal process for 45 nm node and beyond

SoC Res. & Dev. Center, Toshiba Corp. Semicond. Co., Kanagawa, Japan
DOI: 10.1109/.2005.1469245 Conference: VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on
Source: IEEE Xplore


We have investigated millisecond anneal, such as laser spike annealing (LSA) and flash lamp annealing (FLA), which substitute for spike RTA as a dopant activation technology of source/drain extension for 45 nm node. Three key issues of gate leakage current, junction leakage current and pattern dependence were discussed from the integration and CMOSFETs performance viewpoint. We reported that LSA is the leading candidate for 45 nm node and beyond.

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    • "Additional techniques to reduce variability due to lithography include immersion lithography, polarized illumination, and double exposure [46]. Laser annealing also holds the promise of reducing some systematic sources of variation, e.g., variation in transistor characteristics due to local changes in active density [47]. OPC robustness is an important avenue for reducing the variability induced by patterning. "
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    ABSTRACT: Variation in transistor characteristics is increasing as CMOS transistors are scaled to nanometer feature sizes. This increase in transistor variability poses a serious challenge to the cost-effective utilization of scaled technologies. Meeting this challenge requires comprehensive and efficient approaches for variability characterization, minimization, and mitigation. This paper describes an efficient infrastructure for characterizing the various types of variation in transistor characteristics. A sample of results obtained from applying this infrastructure to a number of technologies at the 90-, 65-, and 45-nm nodes is presented. This paper then illustrates the impact of the observed variability on SRAM, analog and digital circuit blocks used in system-on-chip designs. Different approaches for minimizing transistor variation and mitigating its impact on product performance and yield are also described.
    Full-text · Article · Feb 2008 · IEEE Transactions on Electron Devices
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    ABSTRACT: In this work, we report on the integration of 30nm gate length CMOS devices fabricated using laser spike annealing (LSA). Considerably improved short channel effects and drive current (+10% I<sub>on</sub> at constant I<sub>off</sub> for NMOS) are demonstrated on samples using LSA. Excellent I<sub>on</sub>I<sub>off</sub> characteristics (I<sub>on </sub> = 940 muA/mum I<sub>off</sub> = 200 muA/mum for NMOS and I<sub>on</sub> = 390muA/mum I<sub>off</sub> = 50 nA/mum for PMOS at V<sub>dd</sub> = 1 V) are measured that are at the leading edge of the state of the art. Moreover, an enhanced dynamic behavior (-6% in ring oscillator delay) and improved characteristics of high density SRAM bit-cells (+24% I<sub>cell</sub> for the same 1<sub>sb</sub>) are reported. These results demonstrate the potential of LSA in the perspective of 30 nm device integration of a 45 nm bulk CMOS platform
    No preview · Conference Paper · Jan 2006
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    ABSTRACT: In this paper, the potential for sub-10-nm junction formation of partial-melt laser annealing (PMLA), which is a combination of solid-phase regrowth and heat-assisted laser annealing (HALA), is demonstrated. HALA and PMLA are effective for reducing laser-energy density for dopant activation and for improving heating uniformity of device structure. The absence of melting at the dopant profile tail for PMLA results in a negligibly small diffusion at this region. A high activation rate is achievable by melting the upper part of the amorphous-silicon layer. The obtained sheet resistance of 10-nm-deep junctions was about 700 Ω/sq. for both n<sup>+</sup>/p and p<sup>+</sup>/n junctions. These results imply that PMLA is applicable for much shallower junction formation.
    Preview · Article · Jun 2006 · IEEE Transactions on Electron Devices
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