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126 4-900784-00-1 2005 Symposium on VLSI Technology Digest of Technical Papers
8A-1
High Performance 65 nm SOI Technology with Dual Stress Liner and low
capacitance SRAM cell
E. Leobandung, H. Nayakama#, D. Mocuta, K. Miyamoto^, M. Angyal, H. V.- Meer*, K. McStay, I. Ahsan , S. Allen, A. Azuma^, M. Belyansky, R.-V.
Bentum*, J. Cheng*, D. Chidambarrao, B. Dirahoui, M. Fukasawa#, M. Gerhardt*, M. Gribelyuk, S. Halle, H. Harifuchi#, D. Harmon, J. Heaps-Nelson,
H. Hichri, K. Ida#, M. Inohara^, K. Inoue#, K. Jenkins, T. Kawamura#, B. Kim, S.-K. Ku, M. Kumar, S. Lane, L. Liebmann, R. Logan, I. Melville, K.
Miyashita^, A. Mocuta, P. O'Neil, M.-F. Ng*, T. Nogami#, A. Nomura*, C. Norris, E. Nowak, M. Ono^, S. Panda, C. Penny, C. Radens, R.
Ramachandran, A. Ray, S.-H. Rhee*, D. Ryan, T. Shinohara#, G. Sudo^, F. Sugaya#, J. Strane, Y. Tan, L. Tsou, L. Wang, F. Wirbeleit*, S. Wu, T.
Yamashita#, H. Yan, Q. Ye, D. Yoneyama#, N. Zamdmer, H. Zhong*, H. Zhu, W. Zhu, P. Agnello, S. Bukofsky, G. Bronner, E. Crabbé, G. Freeman,
S.-F. Huang, T. Ivers, H. Kuroda#, D. McHerron, J. Pellerin*, Y. Toyoshima^, S. Subbanna, N.Kepler*, and L. Su
IBM System & Technology Group, #Sony Electronics Inc, ^Toshiba America Electronic Components, Inc, *Advanced Micro Devices, Inc,
at IBM Semiconductor Research and Development Center (SRDC), Hopewell Junction, NY 12533
Abstract
A high performance 65 nm SOI CMOS technology is presented
featuring 35 nm gate length, 1.05 nm gate oxide, performance
enhancement from dual stress nitride liners (DSL), and 10 wiring
levels with low-k dielectric offered in the first 8 levels. DSL
enhancement is shown to scale well to 65 nm with larger
enhancement seen than at 90 nm design rules. A high performance
0.65�m2 SRAM cell is also presented. SOI allows the SRAM cell
to use Metal 1 instead of Metal 2 for bit-line wiring, which lowers
the capacitance and improves access times. A functional dual-core
microprocessor test chip containing 76Mb SRAM cache and key
execution units has been fabricated.
Technology Description
Table 1 describes the major ground rules in the technology. A
dense M1 pitch of 180 nm is allowed to improve wiring density.
Significant effort is put into minimizing the gate length variation by
using Alternating Phase Shift Masking (Alt-PSM). Fig. 1 shows that
Alt-PSM reduces the gate length variation due to mask error by 2X
compared to Attenuated Phase Shift.
The gate oxide used in this technology is a 1.05 nm nitrided film.
The thickness is not scaled from 90 nm technology due to chip
power considerations [1]. Fig. 2 shows that the gate oxide 10 year
life-time is acceptable at a power supply > 1.0V.
A device cross section is shown on Fig. 3. A partially-depleted
SOI process is used. The SOI substrate allows higher density
devices by reducing N+/P+ spacing compared to bulk [2]. It also
enhances device performance because the body is floating and
junction capacitance is reduced. Ni silicide is used to reduce the
resistance of a narrow polysilicon gates.
To improve the transistor performance, a dual stress nitride liner
(DSL) process is used [1]. The NFET devices are stressed by a
tensile Middle of Line (MOL) liner film and the PFET devices by a
compressive MOL liner film. This structure is obtained by
depositing a tensile film after silicide formation. Lithography and
etch is used to remove the tensile film from the PFET followed by
deposition of a compressive film over the PFET. Fig. 4 shows that
stress on the device increases as the gate length is reduced. Fig. 5
shows the Ieff (average current at half and full VDD) improvement
with stress for this 65 nm technology in comparison to 90 nm
technology [1]. The improvement is higher in 65 nm technology
which shows the scalability of the DSL stress method.
This technology allows up to 10 levels of copper metallization
with W plug contacts to FEOL layers. An example cross-section is
shown in Fig. 6. The hierarchical BEOL architecture includes an
aggressive 180 nm pitch M1 built in low-k PECVD SiCOH
interlevel dielectric (ILD), 1X, 2X, and 4X minimum pitch wiring
levels also built in SiCOH ILD, and 1.2 um thick wiring levels built
in F-doped TEOS ILD at 1.6 um pitch. With the exception of M1,
the various wiring levels are built using a dual damascene
integration scheme without trench etch stops or hard masks. This
second generation, low-k SiCOH BEOL provides low capacitance
while also enabling low resistance wiring through the hierarchical
structure. Fig. 7 compares the BEOL capacitance as a function of
metal pitch for the 65 nm and 90 nm technology generations and
shows an additional capacitance reduction for the 4X wiring planes
which are built in SiCOH ILD.
Performance and Circuits Results
Multiple threshold voltages (VT) are offered in this 65 nm
technology to optimize the performance and power trade-off. Fig. 8
shows the NFET and PFET device on-current (Ion)as a function of
device off-current (Ioff). At 1V and 200 nA/um Ioff, the NFET DC
Ion is 1.12 mA/um and the PFET DC Ion is 0.63 mA/um. To account
for self-heating in SOI, pulsed I-V is used to measure the AC
switching Ion. The AC switching Ion for NFET is 1.22 mA/um (9%
higher) and PFET is 0.66 mA/um (5% higher). Fig. 9 shows the Vt
roll-off as function of gate length. Well-controlled Short Channel
Effects (SCE) is obtained to gate lengths < 35 nm.
The technology offers a 0.65 um2 SRAM cell. In typical high
performance microprocessors, SRAM access times is a large
contributor to the total chip delay. One way to reduce the SRAM
access time is to reduce the bit-line parasitic capacitance and
resistance. SRAMs in SOI can use lower interconnect levels (Metal
1 instead of Metal 2) for bit-line to reduce the parasitic capacitance
and resistance. Fig. 10 shows the comparison between SRAMs in
SOI and bulk. In SOI, the NFET/PFET is connected using active
area (n+/p+ butted junction) enabling Metal 1 (M1) for bit-line
interconnect. In bulk SRAMs, this connection is done with M1 to
avoid high leakage and shorts, and Metal 2 (M2) is required for bit-
line interconnect [3].
Fig. 11 shows the measured performance benefit of the M1 bit-
line cell compared to M2 bit-line cell. The M1 bit-line cell is 9%
faster than the M2 bit-line cell. One of the potential concerns with
the M1 bit-line cell is the rounding of the active areas which could
cause matched SRAM devices variation from lithography overlay.
The device threshold voltage variation between SRAM devices has
been measured in both M2 and M1 bit-line cells and they show
comparable behavior (Fig. 11). The Static Noise Margin of the M1
bit-line SRAM is 0.237V at 0.9V supply and 0.215V at 0.8V supply
as shown in Fig. 12.
A functional dual-core microprocessor test chip containing a
76Mb SRAM cache and key execution units has been fabricated as
shown in Fig. 13.
References:
[1] H.S. Yang et al., IEDM 2004, p. 1075
[2] Z. Lou et al, IEDM 2004, p. 661
[3] A. Chatterjee et al, IEDM 2004, p.665
Authorized licensed use limited to: RAVIKUMAR RAMACHANDRAN. Downloaded on January 11,2021 at 20:57:39 UTC from IEEE Xplore. Restrictions apply.
127
2005 Symposium on VLSI Technology Digest of Technical Papers
Table 1.Major Ground Rule Table
Rules Pitch
(nm)
Height
(nm)
Contacted gate pitch 250 100
Metal 1 pitch 180 135
1X Metal pitch 200 175
2X Metal pitch 400 350
4X Metal pitch 800 570
8X Metal pitch 1600 1200
0
1
2
3
4
5
6
7
8
220 nm 240 nm 250 nm
Poly Pitch
Gate Length Variation (nm)
Attenuated PhaseShift
Alternating Phase Shift
Fig. 1 Gate Length Variation with
Alternating PSM Lithography
Fig. 2 PFET Gate Oxide Life Time
Fig.3 X-section of the 30 nm gate
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
20 50 80 110 140 170 200
Gate Length (nm)
Normalized Stress (a.u.)
Fig 4. Stress on the devices as function
of gate length
Fig 5. Ieff improvement due to stress for
65 nm technology
Fig. 6 BEOL x-section depicting
10 levels metal interconnect
Fig. 7 BEOL capacitance of 65
nm and 90 nm technology
Fig 8. Device Ion as function of Ioff
NFET
SOI
Fig 9. Device Vt as function of
channel length
in
R
lin
M
Fig. 10 Comparison between SRAM
SOI (Top SEM pictures) with typical
S AM in bulk (layout on bottom). Active
area is used to connect NFET/PFET in
SOI while in bulk Metal 1 is used.
Fig. 11 SRAM cell with M1 bit-
e shows 9% higher frequency than
2 bit-line while the Vt scatter is
comparable.
Fig. 12 SRAM with M1 bit-line
SNM=0.215 at 0.8V
Fig. 13 A functional dual-core
microprocessor test chip containing a
76Mb SRAM cache and key
execution units
30 nm Gate
PFET
PFET NFET
BULK
tal
gate
ive
Me 1
Act area
Authorized licensed use limited to: RAVIKUMAR RAMACHANDRAN. Downloaded on January 11,2021 at 20:57:39 UTC from IEEE Xplore. Restrictions apply.
