TRANSFER OF METAL MEMS PACKAGES USING A WAFER-LEVEL SOLDER
Warren C Welch III and Khalil Najafi
Center for Wireless Integrated Microsystems (WIMS)
University of Michigan, Ann Arbor, Michigan, USA
This paper presents a modular, low profile, wafer-level
encapsulation technology for 0-level MEMS packaging.
Electroplated caps are formed on a carrier wafer then
simultaneously transferred and bonded to a device wafer by
a novel solder transfer method and transient liquid phase
(TLP) bonding technology. The solder transfer method is
enabled by the dewetting of the solder transfer layer from
the carrier wafer, and TLP bonding of the cap to the device
wafer during bonding. The nickel-tin TLP bond and
transfer cycle has a maximum temperature of 300 °C and
lasts about 2.5 hours. This approach has been demonstrated
with nickel caps 5 microns thick, ranging in size from 200
µm 1 mm. They were transferred with a lead-tin transfer
solder layer and bonded with nickel-tin TLP bonding with
greater than 99% transfer yield across the wafer.
In recent years the developments in MEMS packaging
have not kept pace with new achievements in MEMS device
research. Many of the new devices that have been
developed are fragile, suspended, 3D structures that need to
be protected during back end processing steps. RF MEMS
resonators are one example. They require a small gap to
achieve high performance . This makes the devices
susceptible to problems from stiction and particles after they
have been released. These potential problems can
complicate further fabrication steps, such as integration, by
limiting the nature and environment of the final steps to dry
processing in a clean environment. A packaging step
performed right after the devices are released relaxes these
constraints by protecting the devices during the final steps.
A wafer-level thin-film packaging approach offers
many attractive benefits for this packaging step, including: a
small footprint, a hermetic seal, low profile encapsulation,
and low cost . After the devices have been fabricated and
released the thin film package can be applied at the wafer
level while the devices are still in a clean environment. This
eliminates the need for costly die level processing and
provides the back-end protection necessary for high yield.
Thin film packages also reduce processing cost by saving
valuable die area. A thin film packaging approach
previously reported bond rings an order of magnitude
smaller than many conventional bonding technologies in use
today . This is a considerable cost savings when you
consider the size of the devices to be packaged. A typical
MEMS device occupies an area of around 10,000 µm2. A
conventional bond ring surrounding the device occupies an
area 6 times as large. Reducing this bond ring width can
save a large amount of die area. Thin film packaging also
differs from many other wafer-scale packaging approaches
because it can create a reliable hermetic seal and still
maintain a low profile making subsequent integration steps
easier. Quality metal films have low permeability enabling
them to create a hermetic seal with much smaller
thicknesses compared to other materials . Thus, the
package height is reduced from wafer thicknesses of 100’s
of microns down to a low profile thickness of 10’s of
microns without compromising the seal quality. A low-
profile cap relaxes the requirements for the subsequent
integration and assembly steps and offers more options for
the final packaging solution. One approach has achieved
good results with epi-poly as the packaging material, but the
high temperatures required for fabrication make integration
a challenge . Combining the advantages of a thin film
packaging approach with a modular bond and transfer
technique adds process flexibility and eases the integration
of the thin-film package without compromising the device
There are several research efforts pursuing transferred
thin film packaging technology. Most of the efforts have
used polymer bonds to attach packaging caps to the device
substrate [6, 7]. Another effort used solder bonding for
attachment, but it was done at the die level . The
approach reported below combines a metal cap packaging
technology with a transient liquid phase (TLP) metal bond
and implements it on the wafer level. The all-metal bond
and transfer technique is enabled by a novel solder transfer
process that is discussed in the following sections.
The two keys to the solder transfer technique are: the
weakening of the bond between the package cap and the
carrier wafer and the strengthening of the bond between the
package cap and the device wafer. These are accomplished
simultaneously by taking advantage of certain material
properties and interactions at high bonding temperatures.
Figure 1: Cross Section of Package before contact.
Through proper design of the sacrificial solder layer on the
cap wafer and the TLP bond joint on the device wafer, and
by simply making contact between the wafers and raising
the temperature one can bond and transfer the caps. An
illustration of the package cross-section, before contact or
heating the substrates, is shown in figure 1.
The mechanical integrity of a solder joint is a function
of the contact angle between the solder and the surfaces it
bonds together. The relative surface tensions of the solder
and the other materials in the joint will determine this
contact angle. If the surface tension of the solder is higher
than the surface tension of the substrate, the solder will form
a high contact angle with the surface of the substrate and
dewet this surface. This reduces the adhesion strength
between the two materials and results in a weakened bond.
The weakening of a solder bond by dewetting is used in this
transfer approach to facilitate removal of the package caps
from the carrier wafer. During bonding, the elevated
temperatures cause the solder layer to consume its
electroplating seed layer and reveal the surface of the carrier
wafer. The surface tension of the carrier wafer is higher
than the surface tension of the solder so the solder dewets
the carrier wafer and becomes weakly attached (See Fig. 2.)
Figure 2: Solder Transfer layer dewetting.
The selection of a suitable carrier wafer and design of the
solder seed layer are necessary to ensure the sacrificial
solder layer performs properly. First, the carrier wafer needs
to have a surface tension higher than the sacrificial solder
layer. Typical substrates such as silicon or Pyrex wafers
satisfy this requirement. Second, the electroplating seed
layer needs to be a material that is rapidly consumed by the
solder at high temperatures and thin enough to be consumed
in reasonable time. Figure 3 shows the dissolution rates of
several materials in lead-tin solder versus temperature.
Materials like silver and gold are good choices for the seed
layer, because of their high dissolution rates. While the
adhesion strength between the package and the carrier wafer
weakens during bonding, the adhesion between the package
cap and the device wafer will strengthen from the formation
of a TLP bond.
TLP bonding proceeds through 4 stages during
processing (see Fig. 4). First the wafers are brought into
contact, which sandwiches a low melting-point layer, in this
case tin, between two parent metallizations, in this case
nickel. As the temperature increases, the tin starts to melt
(step 2) and form intermetallic compounds (step 3) with the
nickel metals on either side. Further heating (step 4) will
cause the intermetallic compounds to diffuse away from the
joint interface and become a solid solution in the pure nickel
TLP bonds are well suited for this type of packaging
because they can survive much higher temperatures than the
formation temperature. For instance, a Ni-Sn TLP bond is
formed near the melting point of tin (232°C). After the tin
has fully reacted with the nickel to form intermetallic
compounds, the melting temperature of the joint raises to
over 700°C (the melting point of the new intermetallics
compounds) . This packaging step is the first of many
to follow so having a high melting point leaves more final
assembly options open. Some of the final packaging and
integration steps, such as flip chip integration, may require
high temperatures that would not be compatible with this
approach if a solder or polymer bond was used in its place.
Figure 4: The four stages of TLP bonding.
Figure 3: Dissolution rate of metals in Pb-Sn solder .
Fabrication begins on the carrier wafer by evaporating a
thin titanium (50 Å) – gold (500 Å) electroplating seed layer
(see Fig. 5). Gold is used for the seed layer because it is
rapidly dissolved by lead-tin solder and it doesn’t oxidize,
making it easy to electroplate onto. The lead-tin sacrificial
solder is electroplated onto this seed layer into a photoresist
mold. Any solder alloys, such as lead-free solders, could be
used as the solder sacrificial layer as long as they can be
electrodeposited and they satisfy the dissolution rate
requirements for the chosen seed layer. Next, the nickel cap
is formed directly on the sacrificial solder by electroplating
into the same photoresist mold. After the lid is formed, more
photoresist is spun on top of the old resist and the package
rim is defined by photolithography. The nickel oxide that
formed on the cap is removed in a dilute HCl solution
before electroplating the rim to ensure good adhesion. This
completes the fabrication on the carrier wafer.
The device wafer fabrication starts with the deposition
of a titanium (300 Å) – nickel (1500 Å) seed layer. A
photoresist mold is created on top of the seed layer to define
a bond ring around the device. A dip in dilute HCl removes
the nickel oxide from the seed layer before electroplating to
ensure good deposit adhesion. After the bond ring is
electroplated, a layer of tin (1.5 µm) is evaporated onto the
wafer. By sacrificing the electroplating mold, the tin is
removed from all the areas on the wafer except for the top
of the bond rings.
Finally the wafers are aligned and bonded in a Suss SB-
6 wafer bonder. The wafers are loaded and the chamber is
pumped down to vacuum (~5 µtorr) then heated to 300 °C.
After about 2.5 hours at temperature the wafers are allowed
to cool to 50°C under vacuum then the chamber is
pressurized and the wafers removed.
After bonding, the carrier wafer and device wafer are
weakly bound together by the sacrificial solder and package
cap. This bond is easily broken with the tip of a razor blade
and the top wafer removed leaving the caps bonded to the
The process was run with two different substrates for
the device wafer, Pyrex and silicon. The transferred and
non-transferred caps were counted after bonding to measure
the yield. In each case the yield was greater than 99%. The
yield was slightly lower with Pyrex as the device wafer
(1192 out of 1200 caps transferred) vs. silicon (1200 out of
1200 caps transferred). This could be accounted for by the
slight thermal mismatch between silicon and Pyrex. A
picture of a silicon substrate with transferred caps is shown
in Fig. 6. A SEM of the side of a transferred cap is shown
in Fig. 7.
Figure 6: Transferred caps on a silicon wafer.
Figure 7: Side view of a transferred cap.
Figure 5: Cap transfer process overview.
After bonding, the TLP bond composition was analyzed
in a scanning electron microscope with energy dispersive
spectroscopy capabilities. A picture of the bond and the
varying composition is shown in Fig. 8. The formation of
intermetallics was confirmed by the changing ratio of nickel
to tin across the interface. The nickel composition starts at
97% on the top, and then goes to about 50% nickel / 50% tin
near the bond joint, then goes back to 96% on the bottom.
Figure 8: Close-up of TLP bond interface and EDAX
A method of transferring thin-film metal packages with
a novel solder transfer layer has been developed. The
method allows packages to be electroplated on a separate
wafer and later simultaneously transferred and bonded to a
device wafer. This modular approach adds fabrication
flexibility to the packaging process and the device process.
The transfer is accomplished by selective dewetting of a
solder transfer layer and the formation of TLP bond between
the package cap and device wafer. The process was
demonstrated using both Pyrex and silicon substrates as the
device wafer with greater than 99% yield in each case.
This work was supported under DARPA grants
F30602-01-1-0573 and W31P4Q-04-1-R001.
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