Conference Paper

Impact of mask alignment on the tunneling field effect transistor (TFET)

Inst. for Tech. Electron., Tech. Univ. Munich, Germany
DOI: 10.1109/ICMTS.2005.1452216 Conference: Microelectronic Test Structures, 2005. ICMTS 2005. Proceedings of the 2005 International Conference on
Source: IEEE Xplore


The tunneling field effect transistor (TFET) is a standard CMOS process flow compatible device which shows improved short channel characteristics and lower static power consumption. The device is generated by the p-implant layer overlapping the source extension. A test-structure is proposed to investigate the impact of the alignment of the p-implant mask on the device characteristics.

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