Enhanced data retention of damascene-finFET DRAM with local channel implantation and fin surface orientation engineering

Conference Paper · January 2005with6 Reads
DOI: 10.1109/IEDM.2004.1419065 · Source: IEEE Xplore
Conference: Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International


    80nm damascene-finFET (d-finFET) 512M DRAM is fabricated on bulk <100> channel directional wafer (CW). We adopted damascene technology to form the fin only to the channel region of cell array transistor with self-aligned LCI (local channel ion implantation). From the reduced contact resistance, surface treatment, and electron mobility improvement of <100> CW, 50% increased on-current is achieved in d-finFET. Utilizing LCI to d-finFET, junction leakage of the storage node has been reduced. The characteristics of d-finFET and conventional finFET (c-finFET), and <110> CW and <100> CW were compared. Using the d-finFET scheme with LCI, data retention time is further improved from the previous work of c-finFET (Lee et al., 2004).