Conference Paper

Analysis of the effect of LUT size on FPGA area and delay using theoretical derivations

Inst. of Microelectron., Xidian Univ., China
DOI: 10.1109/ISQED.2005.20 Conference: Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
Source: IEEE Xplore


Based on architecture analysis of island-style FPGA, area and delay models of LUT FPGA are proposed. The effect of LUT size on FPGA area and performance is studied. Results show optimal LUT size conclusion from computation models is the same as that of experiments. A LUT size of 4 produces the best area results. A LUT size of 5 provides the better performance.

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Available from: Yintang Yang
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    • "The relationship between logic block architecture and area efficiency was described in [5] [6]. The model in [6] also takes into account cluster-based FPGAs and cluster architecture . "
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    • "There has also been work providing early stage delay values for FPGAs by Manohararajah [19], which uses a lookup table with pre-recorded values of interconnect delays as a function of architecture parameters. The previous work closest to ours is by Gao et al, who relates LUT size to area as well as depth of forming N -LUTs for a non-clustered FPGA [20]. We present a more complete model that considers cluster-based architectures (which are more representative of real FPGAs), and we model a wider range of architectural parameters. "
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    • "A similar problem has been encountered in the design of the FPGA fabrics, when deciding for the optimum look-up tables (LUT) size [Gao, 2005]. It has been found that implementing the design using 4-or 5-input LUTs brings most benefits. "
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