Analysis of the effect of LUT size on FPGA area and delay using theoretical derivations

Conference Paper (PDF Available) · April 2005with36 Reads
DOI: 10.1109/ISQED.2005.20 · Source: IEEE Xplore
Conference: Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
Abstract
Based on architecture analysis of island-style FPGA, area and delay models of LUT FPGA are proposed. The effect of LUT size on FPGA area and performance is studied. Results show optimal LUT size conclusion from computation models is the same as that of experiments. A LUT size of 4 produces the best area results. A LUT size of 5 provides the better performance.