Conference Paper

Dialog and SYNC: A VLSI chip set for timing of the LHCb Muon detector

Università degli studi di Cagliari, Cagliari, Sardinia, Italy
DOI: 10.1109/NSSMIC.2003.1352028 Conference: Nuclear Science Symposium Conference Record, 2003 IEEE, Volume: 1
Source: IEEE Xplore

ABSTRACT

The Muon detector of the LHCb experiment at CERN plays a fundamental role in the first trigger level. It is mainly realized by means of a MWPC technology and consists of about 126,000 front-end channels. High efficiency is necessary both at detector and front-end level to satisfy the trigger requirement of 5 hits per 5 Muon stations with an overall efficiency of 95%. This corresponds to having a single front-end channel detection efficiency of 99% within a time window of 20 ns and also poses the problem of an accurate time alignment of the whole detector. The problem is addressed by designing two custom integrated circuits, named DIALOG and SYNC, realized in the IBM 0.25μm radiation hard technology.

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    • "Therefore to avoid that the tails of the time distribution are assigned to a wrong BX and to reach the required trigger efficiency, it is necessary to center each front-end signal inside the 25 ns time window with a precision of about 2 ns. The Muon Detector time alignment is performed acting both on DIALOG and SYNC [7]. "
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    ABSTRACT: We present a custom integrated circuit, named SYNC, which plays a fundamental role in the time alignment of the LHCb Muon Detector and consequently in the trigger performance. The SYNC is realized in IBM 0.25 μm technology, using radiation-hardening layout techniques. SYNC receives data from the muon detector front-end electronics synchronizing them with the 40.08 MHz LHC clock. The data are tagged with the correct Bunch-Crossing identifier, output to the trigger system and stored in internal memories. The chip integrates 8 time to digital converters with a resolution up to 1 ns to measure the time phase of the input signals with respect to the system clock period. A histogram block can build real time spectra from the TDCs output. A I<sup>2</sup>C interface is implemented to configure and control the device, while a JTAG interface is integrated for boundary-scan purpose. We describe the circuit architecture, its internal blocks and its main modes of operation. Measurements performed on final prototypes are also reported.
    Full-text · Article · Nov 2010 · IEEE Transactions on Nuclear Science
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    • "The fine time information inside the 25 ns gate, measured by a 4-bit TDC ASIC (SYNC [4]) on the ODE boards, is added and the data are transmitted via optical links to the TELL1 board [5] and from the TELL1 to the DAQ system. "
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    ABSTRACT: The LHCb Muon system performance is presented using cosmic ray events collected in 2009. These events allowed to test and optimize the detector configuration before the LHC start. The space and time alignment and the measurement of chamber efficiency, time resolution and cluster size are described in detail. The results are in agreement with the expected detector performance.
    Full-text · Article · Sep 2010 · Journal of Instrumentation
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    [Show abstract] [Hide abstract]
    ABSTRACT: We present a custom integrated circuit, named SYNC, which is a fundamental building block in the front-end architecture of the LHCb muon detector. SYNC is realized in IBM 0.25 μm technology, using radiation hardening layout techniques. Each SYNC integrates the complete front-end L0 stage, consisting of a buffer and a derandomizer and an interface to the L1 stage. It also integrates custom TDCs, one per each input channel, having a time resolution of 1.5 ns. Many monitoring and diagnostic facilities are also integrated on the chip. We describe the circuit architecture, its internal blocks and its main modes of operation.
    Preview · Conference Paper · Nov 2004
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