Functional devices and circuits based on Resonant Tunnelling
Diodes (RTDs) are receiving much attention since they allow high
speed and/or low power operation. RTDs exhibit a negative differ-
ential resistance in their current-voltage characteristic which can
be exploited to significantly increase the functionality imple-
mented by a single gate in comparison to other technologies. In
particular they have proven to efficiently implement threshold
gates which are a generalization of conventional boolean gates.
Suitable logic synthesis tools are required to handle these complex
building blocks in order to translate the advantages of this emer-
gent technology to the circuit and system levels. This paper
describes an efficient approach to the automatic design of net-
works of threshold gates from functional specifications. Results
on wide used logic functions and standard benchmark circuits are
Resonant tunnelling diodes (RTDs) are very fast non lin-
ear circuit elements which are used in high speed low-power
circuits. Switching speeds at room temperature in the order of
one picosecond have been reported for these devices. In addi-
tion, RTDs exhibit a negative differential resistance (NDR)
region in their current-voltage characteristics which can be
exploited to significantly increase the functionality imple-
mented by a single gate in comparison to MOS and bipolar
technologies, thus reducing circuit complexity and power
consumption. Many of them rely on utilizing the latching
property of the clocked series connection of a pair of RTDs
(MOBILE) arising from their NDR characteristic. In general,
MOBILE based logic families combine the basic pair of se-
ries-connected RTDs with different three terminal devices to
achieve input-output isolation and functionality. Most report-
ed working circuits have been fabricated in III/V while Si-
based RTDs is an area of active research.
The MOBILE operating principle  is very well suited
to implement Threshold Gates (TGs) . RTD-based TGs
have been fabricated and have demonstrated high speed and
robust operation , . The power of the threshold gates lies
in the intrinsic complex functions implemented by such
gates, which allows for realizations that require less threshold
gates than standard boolean logic gates. A number of theoret-
ical results show that polynomial-size, bounded level net-
works of threshold gates can implement functions that require
unbounded level networks of standard logic gates In particu-
lar, important functions like multiple-addition, multiplica-
tion, division, or sorting can be implemented by polynomial-
size threshold circuits of small constant depth .
Translating the advantages of this emergent technology to the
circuit and system levels could be limited by the lack of automatic
synthesis procedures. Many logic algorithm exist targeting con-
ventional logic gates but few have been specifically developed for
TGs. The problem was addressed as early as the beginning of the
70’s, but unfortunately it seems that almost nothing has been done
since then. LSAT algorithm  inspired from techniques used in
classical two-level minimization of logic circuits, a multi-level
approach  and a very recent work  are remarkable excep-
This paper describes an efficient approach to the automatic
design of networks of threshold gates from functional especi-
fications. Set of solutions are described by discrete functions
and represented by Multi-valued Decision Diagrams (MDDs)
which are a variant of BDDs. The problem of designing a
optimum network of TGs is transformed in a satisfiability
problem. The rest of the paper is organized as follows. Sec-
tion II formally defines the concept of threshold logic and
establish the formulation of the problem of logic synthesis
for TGs on which our CAD tool relies. Section III describes
the implementation of the proposed approach. Section IV
reports experimental results. Finally, Section V gives some
A Threshold Logic Synthesis Tool for RTD
María J. Avedillo and José M. Quintana
Instituto de Microelectrónica de Sevilla, IMSE-CNM,
Universidad de Sevilla, SPAIN.
A novel logic synthesis tool for the synthesis of general bool-
ean functions using threshold gates has been described. It is based
on the representation of the discrete characteristic function repre-
senting the set of solutions to the problem of implementing a
given function with a multi-layer feed-forward network of thresh-
old functions with M gates. Since this exact solution is not practi-
cal when the number of inputs increases, the circuit is partitioned
in clusters with are then exactly solved. Preliminary results using
an standard partitioning algorithm, that is, non specifically opti-
mized for the threshold network implementation it is targeted, are
Addressing the problem of synthesis with threshold gates is
extremely important for the success of emergent technologies like
RTDs which application could be limited by the lack of CAD
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Table III:Results of LTHRES with standard partition algorithm
# I # O
alu2 106 218174
b941 21 8264
cm138a68 19 10
cm42a4 10 2011
decod5 16 3216
cm151a 122 12 13
cu 141135 24
cmb 164 32 18
cm163a 165 2221
cm150a 211 4024