Conference Paper

A power constrained simultaneous noise and input matched low noise amplifier design technique

Inf. & Commun. Univ., Daejeon, South Korea
DOI: 10.1109/ISCAS.2004.1328995 Conference: Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on, Volume: 4
Source: IEEE Xplore


In this paper, very simple and insightful sets of noise parameters expressions for a power-constrained simultaneous noise and input matching (PCSNIM) CMOS LNA design technique are newly introduced. Based on the noise parameters expression, the design principle, advantages, and limitations are clearly explained. The proposed LNA is optimized for low voltage, low power 900 MHz Zigbee applications based on 0.25 μm CMOS technology. Measurement results show a power gain of 12 dB, NF and NFmin of 1.35 dB, and IIP3 of -4 dBm while dissipating the DC current of 1.6 mA (only 0.7 mA for NMOS transistor) at a supply voltage of 1.25 V.

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    • "Figure 2 shows the small-signal equivalent of the input circuit including noise models. In Figure 2, the effects of M2 on the noise and frequency response are neglected as well as the parasitic resistance of gate, body, source, drain terminals, and the gate-drain capacitance of M1[5]. Figure 2. Small-signal equivalent of input circuit According to some lengthy algebraic derivations from [9], the noise parameters for ISD cascode amplifier with Cex capacitor can be expressed as: "
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    ABSTRACT: This paper presents a fully integrated two-stage narrow-band low noise amplifier which optimized to work in 2.45 GHz center frequency. The topology of inductive source degenerated cascode based on power-constrained simultaneous noise and input matching (PCSNIM) technique has been adopted to make the LNA suitable for low power applications based on 0.13 μm Silterra CMOS technology. Post layout simulation results show power gain of 22 dB, NF of 2.06 dB, S11 of -19 dB and S22 of -12 dB while consuming the DC current of 4 mA at supply voltage of 1.2 V.
    Full-text · Conference Paper · Oct 2012
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    ABSTRACT: This paper presents a design of low power CMOS LNA(Low Noise Amplifier) for 2.4 GHz ZigBee applications that is a promising international standard for short area wireless communications. The proposed circuit has been designed using TSMC CMOS process technology and two stage cascade topology by current reuse technique. Two stage cascade amplifiers use the same bias current in the current reused stage which leads to the reduction of the power dissipation. LNA design procedures and the simulation results using ADS(Advanced Design System) are presented in this paper. Simulation results show that the LNA has a extremely low power dissipation of 1.38mW with a supply voltage of 1.0V. This is the lowest value among LNAs ever reported. The LNA also has a maximum gain of 13.38dB, input return loss of -20.37dB, output return loss of -22.48dB and minimum noise figure of 1.13dB.
    Preview · Article · Jan 2006
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    ABSTRACT: A CMOS RF receiver for L1/L1F and L5/E5a dual-band GPS/Galileo system is designed in a 0.13 m standard CMOS process. It can be fully integrated in System-on-Chip (SoC) solution for GPS and Galileo. The receiver includes a low-noise amplifier (LNA), down-conversion mixers, channel selection filters (CSF), 2-bit analog-to-digital converters (ADC) and the full phase-locked-loop (PLL) synthesizers as well as on-chip voltage-controlled-oscillator (VCO). The dual-band LNA achieves a noise figure (NF) of 2.2 dB and a gain of 16 dB for each band. The PLL exhibits phase noise of -90 dBc/Hz at 100 kHz offset frequency. The receiver consumes 26 mW for a supply voltage of 1.2 V while occupying a 3times3.8 mm<sup>2</sup> die area including ESD I/Q pads.
    No preview · Conference Paper · Dec 2008
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