Conference Paper

System design issues for 3D system-in-package (SiP)

Inst. of Electron., Tampere Univ. of Technol., Finland
DOI: 10.1109/ECTC.2004.1319401 Conference: Electronic Components and Technology Conference, 2004. Proceedings. 54th, Volume: 1
Source: IEEE Xplore

ABSTRACT

Development in electronics is driven by device and market needs. This paper focuses on system design issues for three-dimensional packaging technology and discusses interconnection density, material compatibility, thermal management, electrical requirements, related to delay and noise. Microelectronics packaging has to provide all future devices, such as electronics, actuators, sensors, antennas, optical/photonic, MEMS, and biological solutions. However, a 3D package is a cost effective solution to save placement and routing area on board using several IC processes in the same module. System-in-package (SiP) can combine all the electronic requirements of a functional system or a subsystem in one package. The driving force is integration without compromising individual chip technologies. In this work, a stacked system-in-package structure has been studied. The thermo-mechanical behavior of packages has been analyzed by finite element analysis (FEA) and the correlation between the experimental test results and the modeling was analyzed. A stacked 3D package can contain multiple heat sources that produce high power density. Therefore, thermal management needs extra attention to ensure safe operating temperatures under all conditions. The thermal behavior of the package was modeled using FEA and a boundary condition independent (BCI) compact thermal model (CTM) was built based on simulation results. In addition, high-speed signal and interfering environment set quite stringent requirements for 3D devices. Crosstalk between vertical connections was simulated and measured. Measurements of S-parameters were done using a network analyzer. The frequency range was 45 MHz to 20 GHz.

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    • "Health monitoring can also improve the cost-effectiveness of inspection and maintenance of the systems. With the increasing miniaturization and heterogeneous integration of electronic systems enabled by the system-in-package (SiP) technology [1] [2] [3], it is becoming difficult to conduct electrical test using the conventional This work was supported by the Innovative Electronics Manufacturing Research Centre (IeMRC) of the UK Engineering and Physical Sciences Research Council (EPSRC) under grant SP/06/03/07, and Scottish Enterprise and the European Fund through the Proof of Concept Programme (PoCP). C. H. Wang is with the School of Engineering and Physical Sciences, Heriot Watt University, Edinburgh EH14 4AS, UK. (Tel & Fax: +44 1314513903, Email: c.wang@hw.ac.uk). "
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    ABSTRACT: This paper presents the development of integrated sensors for health monitoring applications in microsystems. Intelligent health monitoring is an emerging method for early diagnostic of the status or ¿health¿ of electronic systems and products under operation based on embedded tests. In this approach miniature sensors are used to monitor the key parameters of the package/system for example temperature, pressure, stress and humidity. Based on the outputs of the sensors stimuli are then used to test the responses of the system to determine its behavior. Thus early warning of system fault or failure can be obtained and measures taken for repair work or replacement of the system. We have been developing integrated sensors on a chip for health monitoring applications in electronic systems. Integrated sensors on LiNbO<sub>3</sub> and silicon substrates are being investigated. In this paper we report the development of discrete sensors and the integration methods. Thin film temperature sensor arrays have been developed and tested as embedded sensors in substrate assemblies. SAW based low cost sensors have been designed and fabricated for humidity monitoring. Methods for sensor integration and the preliminary results are described.
    Full-text · Conference Paper · Dec 2009
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    • "Different forms of 3-D integration (not to scale). (a) System-in-package [32] and (b) a 3-D circuit with dense through silicon vias [8], [9]. Two different bonding styles, front-to-front and back-to-front, are illustrated. "
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    ABSTRACT: Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for two-dimensional circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits while considering different forms of vertical integration, such as system-in-package and 3-D ICs with fine grain vertical interconnections. Global signaling issues, such as clock and power distribution networks, are further exacerbated in vertical integration due to the limited number of package pins, the distance of these pins from other planes within the 3-D system, and the impedance characteristics of the through silicon vias (TSVs). In addition to these dedicated networks, global signaling techniques that incorporate the diverse traits of complex 3-D systems are required. One possible approach, potentially significantly reducing the complexity of interconnect issues in 3-D circuits, is 3-D networks-on-chip (NoC). Design methodologies that exploit the diversity of 3-D structures to further enhance the performance of multiplane integrated systems are necessary. The longest interconnects within a 3-D circuit are those interconnects comprising several TSVs and traversing multiple physical planes. Consequently, minimizing the delay of the interplane nets is of great importance. By considering the nonuniform impedance characteristics of the interplane interconnects while placing the TSVs, the delay of these nets is decreased. In addition, the difference in electrical behavior between the horizontal and vertical interconnects suggests that asymmetric structures can be useful candidates for distributing the clock signal within a 3-D circuit. A 3-D test circuit fabricated with a 180 nm si- - licon-on-insulator (SOI) technology, manufactured by MIT Lincoln Laboratories, exploring several clock distribution topologies is described. Correct operation at 1 GHz has been demonstrated. Several 3-D NoC topologies incorporating dissimilar 3-D interconnect structures are reviewed as a promising solution for communication limited systems-on-chip (SoC). Appropriate performance models are described to evaluate these topologies. Several forms of vertical integration, such as system-in-package and different candidate technologies for 3-D circuits, such as SOI, are considered. The techniques described in this paper address fundamental interconnect structures in the 3-D design process. Several interesting research problems in the design of 3-D circuits are also discussed.
    Full-text · Article · Feb 2009 · Proceedings of the IEEE
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    • "Different forms of 3-D integration (not to scale). (a) System-in-package [32] and (b) a 3-D circuit with dense through silicon vias [8], [9]. Two different bonding styles, front-to-front and back-to-front, are illustrated. "
    [Show abstract] [Hide abstract]
    ABSTRACT: Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manu- facturing technologies. Advanced design methodologies for two-dimensionalcircuits are notsufficienttomanagetheadded complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added com- plexityandinherentheterogeneityof3-Dcircuitsarenecessary. These 3-D design methodologies should support robust and reliable3-Dcircuitswhileconsideringdifferentformsofvertical integration, such as system-in-package and 3-D ICs with fine grain vertical interconnections. Global signaling issues, such as clock and power distribution networks, are further exacerbated in vertical integration due to the limited number of package pins, the distance of these pins from other planes within the 3-D system, and the impedance characteristics of the through silicon vias (TSVs). In addition to these dedicated networks, global signaling techniques that incorporate the diverse traits of complex 3-D systems are required. One possible approach, potentially significantly reducing the complexity of intercon- nectissuesin 3-Dcircuits,is3-Dnetworks-on-chip(NoC).Design methodologies that exploit the diversity of 3-D structures to further enhance the performance of multiplane integrated systems are necessary. The longest interconnects within a 3-D circuit are those interconnects comprising several TSVs and traversing multiple physical planes. Consequently, minimizing the delay of the interplane nets is of great importance. By considering the nonuniform impedance characteristics of the interplane interconnects while placing the TSVs, the delay of these nets is decreased. In addition, the difference in electrical behavior between the horizontal and vertical interconnects suggests that asymmetric structures can be useful candidates for distributing the clock signal within a 3-D circuit. A 3-D test circuit fabricated with a 180 nm silicon-on-insulator (SOI) technology, manufactured by MIT Lincoln Laboratories, explor- ing several clock distribution topologies is described. Correct operation at 1 GHz has been demonstrated. Several 3-D NoC topologies incorporating dissimilar 3-D interconnect structures arereviewedasapromisingsolutionforcommunicationlimited systems-on-chip (SoC). Appropriate performance models are described to evaluate these topologies. Several forms of vertical integration, such as system-in-package and different candidate technologies for 3-D circuits, such as SOI, are considered. The techniques described in this paper address fundamental interconnect structures in the 3-D design process. Several interesting research problems in the design of 3-D circuits are also discussed.
    Full-text · Article · Jan 2009 · Proceedings of the IEEE
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