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Future memory technology including emerging new memories

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Abstract

There have been concerns about how far we can extend the so far so successful conventional semiconductor memories Such as DRAM, SRAM and Flash memory and what will be the future directions of memory development. In this article, we will review the key technical limits of conventional memory scaling and the directions to overcome the problem. In addition, we will review the technical challenges and opportunities of emerging. new memories such as ferroelectric RAM (FRAM), magnetic RAM (MRAM) and phase change RAM (PRAM) which has been recently focused as candidates for ideal memory which can solve the problems of conventional memories.

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... But, the increased doping concentration is accompanied with the increase of electric field across the junction boundary ( Figure 2) and the increase of junction leakage current. This junction leakage current results in decrease of data retention time (Kim and Koh, 2004). Source: Kim and Koh (2004) As junction electric field increases rapidly, significant degradations of data retention time below 100 nm node are expected. ...
... This junction leakage current results in decrease of data retention time (Kim and Koh, 2004). Source: Kim and Koh (2004) As junction electric field increases rapidly, significant degradations of data retention time below 100 nm node are expected. It is possible to overcome these problems by utilising the non-planar cell transistors. ...
... Using recessed channel array transistor (RCAT) as shown in Figure 3, we can increase the effective channel length and reduce doping concentration without adding significant process complexity (Kim et al., 2003). Kim and Koh (2004) In order to scale down the DRAM technology below 50 nm node and better performance with large cell transistor current, we need another breakthrough in technology. Using FinFET-type cell transistors, we can control the channel punch-through by adjusting the channel silicon thickness. ...
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... This low performance characteristic for random write requests should be clearly problematic in future systems which require more complex and frequent random access requests. Recently, PRAM (Phase-change RAM) [2,3] device, which supports fast byte-or word-access capability without erasebefore-program requirement like normal DRAMs, is introduced as an next generation non-volatile memory device and it will be commercially announced by the several chip vendors very soon [17] . At a first glance, the PRAM may seem to be an ideal nonvolatile storage device which can completely overcome the physical constraints of traditional flash memory devices. ...
... In this section, we revisit the mapping algorithms in NAND flashbased storage architecture and the related work about hybrid storage approaches with next-generation NVRAMs (Non-volatile RAMs) [2,3,4], separately. ...
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ABSTRACT NAND flash-based storage is widely used ,in embedded ,systems due to its numerous benefits: low cost, high density, small form factor and so on. However, NAND flash-based storage is still suffering from ,serious performance degradation ,for random ,or small size write access. This degradation mainly ,comes,from the physical constraints of NAND flash: erase-before-program ,and different unit size of erase and program,operations. To overcome these constraints, we propose touse PRAM (Phase-change RAM) which supports advanced,features: fast byte access capability and no requirement for erase-before-program. In this paper, we focus on developing a high-performance NAND flash-based storage system by maximally exploiting the advanced feature of PRAM, in terms of performance and wearing out. To dothis, we first propose a new hybrid storage architecture which consists of PRAM and NAND flash.Second, we devise two novel software schemes ,for the proposed ,hybrid storage architecture; FSMS (File System Metadata Separation) and hFTL (hybrid Flash Translation Layer). Finally, we demonstrate that our hybrid architecture increases the performance ,up to ,290% and doubles the lifespan compared ,to the ,existing NAND flash only storage systems. Categories and Subject Descriptors
... STT-RAM has a very good write speed with a good read speed. It has non-volatile in nature such as Flash memory [1] [2] [3]. Comparison of STT-RAM with other memories's technology shown in TABLE 1. STT-RAM has a wide range of application and it is CMOS capable to [3]. ...
... It has non-volatile in nature such as Flash memory [1] [2] [3]. Comparison of STT-RAM with other memories's technology shown in TABLE 1. STT-RAM has a wide range of application and it is CMOS capable to [3]. ...
... That is, a grid of 11 by 12 such cards would be sufficient -or more likely a single 3D chip with transistors stacked on top of each other would be used. It is notable that existing flash RAM is based on NAND technology and that replacement technologies have already been proposed (Kim and Koh 2004). ...
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... Ultimately, there is a scaling limit to FLASH and engineers are researching the next generation of memory technology. 15 In studying FLASH and other emerging non-volatile memory options, students learn about the electrical properties of metals and semiconductors, semiconductor doping, p-n junctions and transistors, and magnetic materials. Details of this module, including class by class learning objectives have been published previously. ...
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... The next-generation nonvolatile memory types such as phase-change RAM (PRAM), ferroelectric RAM (FeRAM), and magnetic RAM (MRAM) are known not only to be as fast as DRAM in terms of both read and write operations, but also as inplace updating is possible. The access times for DRAM, next-generation NVRAM, and NAND flash memory are summarized in Table 1 [8], [9]. ...
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... This will set it apart from other file systems, so it will be an important consideration when designing a search mechanism. The properties of MRAM make it superior to many other technologies [3]. It is nonvolatile, which means that the data will remain the same when there is no power available. ...
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The Linking File System (LiFS) is an ex- perimental file system being developed by UC Santa Cruz. It allows users to define re- lational links between files with a semantic meaning. This paper explores the possibili- ties of a query language to find information in LiFS, while taking advantage of links. The results show that a very powerful language can be defined and implemented. The im- plementation uses rules to "walk" the direc- tory structure to search for files. This style of searching is very inecient in larger file sys- tems, even when the search is restricted to a small subdirectory. A new searching idea will be needed to implement this query language eciently.
... A flash device is composed of several planes, each of which has a set of blocks. In turn, each block is divided into pages.Figure 2a There are three operations which should be executed on a flash device: read, erase and program [Kim and Koh 2004]. A read operation may randomly occur anywhere in a flash device. ...
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The aim of this paper is to give a thorough overview of flash memory cells. Basic operations and charge-injection mechanisms that are most commonly used in actual flash memory cells are reviewed to provide an understanding of the underlying physics and principles in order to appreciate the large number of device structures, processing technologies, and circuit designs presented in the literature. New cell structures and architectural solutions have been surveyed to highlight the evolution of the flash memory technology, oriented to both reducing cell size and upgrading product functions. The subject is of extreme interest: new concepts involving new materials, structures, principles, or applications are being continuously introduced. The worldwide semiconductor memory market seems ready to accept many new applications in fields that are not specific to traditional nonvolatile memories
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The development status for ovonic unified memory (OUM), a phase change, nonvolatile semiconductor memory technology for very large scale integration (VLSI) stand-alone memory and embedded applications is discussed. A 4 Mb VLSI test memory, with 0.18 μm 3V CMOS is used as a developmental tool. The characterization of OUM for high density, low voltage, high cycle-count nonvolatile memory applications with short programming times, is also reviewed. OUM provides advantages in cell size, process complexity, cost, write times, cycling, cell energy consumption during write and direct over-write.
Article
We have introduced the concept of floating-gate interference in flash memory cells for the first time. The floating-gate interference causes V-T shift of a cell proportional to the V-T change of the adjacent cells. It results from capacitive coupling via parasitic capacitors around the floating gate. The coupling ratio defined in the previous works should be modified to include the floating-gate interference. In a 0.12-mum design-rule NAND flash cell, the floating-gate interference corresponds to about 0.2 V shift in multilevel cell operation. Furthermore, the adjacent word-line voltages affect the programming speed via parasitic capacitors.
Conference Paper
By developing a chalcogenide memory element that can be operated at low writing current, we have demonstrated the possibility of high-density phase-change random access memory. We have investigated the phase transition behaviors as a function of various process factors including contact size, cell size and thickness, doping concentration in chalcogenide material and cell structure. As a result, we have observed that the writing current is reduced down to 0.7 mA.
Article
This paper focuses on approaches to continuing CMOS scaling by introducing new device structures and new materials. Starting from an analysis of the sources of improvements in device performance, we present technology options for achieving these performance enhancements. These options include high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET, and strained-silicon FET. Nanotechnology is examined in the context of continuing the progress in electronic systems enabled by silicon microelectronics technology. The carbon nanotube field-effect transistor is examined as an example of the evaluation process required to identify suitable nanotechnologies for such purposes.
Article
Ferroelectric devices have been developed for future memory devices due to their ideal memory properties such as non-volatility, fast access time, and low power consumption. Several integration issues for commercial ferroelectric devices have been overcome or are being resolved by novel process technology and design technology. The process technology is combined with ferroelectric material technology, electrode technology, etching technology, hydrogen barrier technology, barrier and plug technology, and backend technology. The advanced process technologies are enhanced by developing its own design technology. In recent few years, low density ferroelectric random access memory (FRAM) products start to gradually but progressively penetrate into memory and smart card market, and the ferroelectric devices are developed to 32 Mb FRAM with 0.25 μm design rule and triple metallization. In this paper, it is reviewed how to integrate the ferroelectric devices for producing commercial products.
Conference Paper
In this paper, a highly manufacturable 512M FinFET DRAM with novel body tied FinFET cell array transistor on bulk Si substrate has been successfully integrated and the characteristics were compared with RCAT (Recess Channel Array Transistor) and planar cell array transistor DRAM for the first time. We also propose the NWL (Negative Word Line) scheme with low channel doping body tied FinFET for a highly manufacturable FinFET DRAM for sub 60nm technology node.
Conference Paper
The Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub> (GST) thin film is well known to play a critical role in PRAM (Phase Change Random Access Memory). Through device simulation, we found that high-resistive GST is indispensable to minimize the writing current of PRAM. For the first time, we tried to increase the GST resistivity by doping nitrogen. Doping nitrogen to GST successfully reduced writing current. Also, the cell endurance has been enhanced with grain growth suppression effect of dopant nitrogen.
Conference Paper
In this paper, the Phase Change Random Access Memory (PRAM, also known as Ovonic Unified Memory-OUM) cell, which has an extremely small and reproducible contact area and improved thermal environment, was fabricated and electrically characterized. The memory cell successfully operates with 30 ns pulses of 0.20 mA for RESET (high resistive) state and 0.13 mA for SET (low resistive) state. This is the best record of the published data.
Conference Paper
For the first time, 512 Mb DRAMs using a Recess-Channel-Array-Transistor(RCAT) are successfully developed with 88 nm feature size, which is the smallest feature size ever reported in DRAM technology with non-planar array transistor. The RCAT with gate length of 75 nm and recessed channel depth of 150 nm exhibits drastically improved electrical characteristics such as DIBL, BV<sub>DS</sub>, junction leakage and cell contact resistance, comparing to a conventional planar array transistor of the same gate length. The most powerful effect using the RCAT in DRAMs is a great improvement of data retention time. In addition, this technology will easily extend to sub-70 nm node by simply increasing recessed channel depth and keeping the same doping concentration of the substrate.
Conference Paper
This work is a report on high-performance MRAM technology. 0.4×0.8 μm<sup>2</sup> MTJ elements were successfully integrated with 0.35 μm CMOS technology without process-induced damage. A magnetoresistance (MR) ratio of more than 55% and the read/write operating point were obtained by introducing an improved magnetic tunnel junction (MTJ) material. The short-pulse writing in combination with an improved cell structure suggests that MRAM has a great deal of potential for low power applications.
Article
The accelerating pace of CMOS scaling is rapidly approaching the fundamental limits of MOSFET performance, even as the projected size of a high-performance and manufacturable MOSFET technology is currently being extended with growing confidence to the 22-nm node (featuring a 9-nm physical gate length). The new 2001 International Technology Roadmap for Semiconductors currently projects the industry to reach this node in 2016. However, this forecast assumes the traditional industry node-cycle cadence of a quadrupling of the number of transistors every three years for DRAMS and a return to the three-year cycle in 2004 for MPUs and ASICs. During the past several years the node cycles for MPUs have been accelerated to occur within two-year periods. This pace will bring the microelectronics industry to the end of silicon CMOS technology scaling sometime not later than 2016, and maybe as soon as 2010. The new Emerging Technologies section of the 2001 ITRS offers guidance on both sides of this problem: nanoelectronics for memory, logic, and information-processing architectures could possibly extend the time frame of the ITRS beyond CMOS
Article
With the promise of nonvolatility, practically infinite write endurance, and short read and write times, magnetic tunnel junction magnetic random access memory could become a future mainstream memory technology.
Article
Many challenges emerge as the DRAM enters into a generation of the gigabit density era. Most of the challenges come from the shrink technology which scales down minimum feature size by a factor of 0.84 per year. The need for higher performance to narrow the bandwidth mismatch between fast processors and slower memories and lower power consumption drives the DRAM technology toward smaller cell size, faster memory cell operation, less power consumption, and longer data retention times. In addition, increasingly complicated wafer processing requires simple process. In this paper, the challenges brought from the extremely small minimum feature, high performance, and simple wafer processing will be discussed. The solutions to overcome the challenges will be described focusing on the memory cell scheme, lithography, device, memory cell capacitor, and metallization
Article
Magnetoresistive random access memory (MRAM) technology combines a spintronic device with standard silicon-based microelectronics to obtain a combination of attributes not found in any other memory technology. Key attributes of MRAM technology are nonvolatility and unlimited read and write endurance. Magnetic tunnel junction (MTJ) devices have several advantages over other magnetoresistive devices for use in MRAM cells, such as a large signal for the read operation and a resistance that can be tailored to the circuit. Due to these attributes, MTJ MRAM can operate at high speed and is expected to have competitive densities when commercialized. In this paper, we review our recent progress in the development of MTJ-MRAM technology. We describe how the memory operates, including significant aspects of reading, writing, and integration of the magnetic material with CMOS, which enabled our recent demonstration of a 1-Mbit memory chip. Important memory attributes are compared between MRAM and other memory technologies.
Article
A low-power 1-Mb magnetoresistive random access memory (MRAM) based on a one-transistor and one-magnetic tunnel junction (1T1MTJ) bit cell is demonstrated. This is the largest MRAM memory demonstration to date. In this circuit, the magnetic tunnel junction (MTJ) elements are integrated with CMOS using copper interconnect technology. The copper interconnects are cladded with a high-permeability layer which is used to focus magnetic flux generated by current flowing through the lines toward the MTJ devices and reduce the power needed for programming. The 25-mm<sup>2</sup> 1-Mb MRAM circuit operates with address access times of less than 50 ns, consuming 24 mW at 3.0 V and 20 MHz. The 1-Mb MRAM circuit is fabricated in a 0.6-μm CMOS process utilizing five layers of metal and two layers of poly.
Emerging memories: reclvdogies om1 rreuds
  • Betty Prince
Betty Prince, Emerging memories: reclvdogies om1 rreuds, Klu\ver Academic Publishers, Massachusetts, 2002.
Flash memoiy cells -An Ovcrvic~
  • P Pavan
P. Pavan et al., ''Flash memoiy cells -An Ovcrvic~.", Pi-uc.
Improvement of read and write Dec. 2003. operations in MRAM structured for high densiry
  • W C Jeong
W.C. Jeong et al., " Improvement of read and write Dec. 2003. operations in MRAM structured for high densiry ", subimtted to VLSl Tech. Dig., 2004.
A Novel SONOS Structure of Si02/SiN/A1203 with TaN Metal Gate for Multi-gigs Bit Flash Memories
  • C H Lee
A O.18um 4Mb toggling MRAM
  • M Durlam
0.1um-rule MRAM development using double-layered hard mask
  • K Tsuji
0) for Improved MOSFET Stability
  • H.-H Tseng