Source/drain engineering for sub 100-nm technology node

Conference Paper · October 2002with14 Reads
DOI: 10.1109/IIT.2002.1257925 · Source: IEEE Xplore
Conference: Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on
ITRS2001 indicates 25-nm physical gate length and 10-17-nm extension depth are required in 65-nm technology node for high performance application. It means resultant requirement of precisely controlled conventional process and new material and process introduction. Though ion implantation and spike RTA are still base line technology for doping, it should be carefully optimized in process integration avoiding implantation-induced damage and transient enhanced diffusion. Careless process sequence might cause undesired enlargement of junction depth even in LPCVD temperature annealing. Sidewall scaling is also necessary to reduce source and drain parasitic resistance and it relates to the contact junctions and silicidation process. Cobalt salicide is widely used in recent technology node. However, its silicon consumption in silicidation process requires relatively deep contact junctions and tends to cause the interference of the contact junction to the channel region. Therefore, lower silicon consumption silicide material such as nickel SALICIDE is one of the solutions. NiSi silicidation can be performed at low temperature and silicon consumption is about 80% of CoSi2 silicide under the same silicide thickness condition. Additionally, more structural approach like elevated source/drain using selective silicon or silicon-germanium will be introduced to solve severer constraints.
    • "The Y-parameters thus extracted after de-embedding is given by [Y int ] representing the intrinsic Y-parameter of the devices, which in detail is reported in [20]. The intrinsic AC small signal model parameters in terms of [Y int ] are tabulated inTable 1. Utilising the [Y int ], the intrinsic RF parameters of the device are extracted for several, gate and drain, bias voltages. "
    [Show abstract] [Hide abstract] ABSTRACT: In this study, a look up table (LUT) is developed to extract the intrinsic RF parameters of underlap DG MOSFET (UDG-MOSFET) including the non-quasi-static (NQS) effect. The LUT-based approach proposed; can accurately extract complex RF parameters of UDG-MOSFET under different bias conditions, necessary for RF circuit simulations by an interpolation algorithm. The RF parameters including intrinsic gate to drain capacitance (Cgd), gate to source capacitance (Cgs), gate to drain resistance (Rgd), gate to source resistance (Rgs), gate to source transconductance (gm), drain to source transconductance (gds), transport delay (tm), capacitance because of DIBL (Csdx) and inductance because of transport delay (Lsd), cut-off frequency (fT) and maximum frequency of oscillation (fmax) are extracted using LUT approach. Parameters extracted using LUT are compared with simulated data, considering the NQS effect, and are found in good agreement. For RF circuit applications a low-noise amplifier is designed, with the UDG-MOSFET, operating at a tuned frequency of 10 GHz.
    Full-text · Article · Nov 2014
    • "At the time of RF parameter extraction the V ds is fixed at 0.55 V accordance with to ITRS 2008 [18], the V gs is fixed at 1.0 V and the frequency is varied up to 100 GHz. The U-DMG-DG NMOSFET device can be fabricated by following the steps for fabricating the standard Fin-FETs [21] , with an additional step of introducing the underlap regions on the source and drain sides of the channel using the tilt ion implantation technique [22] . The feasibility of the structure is illustrated in [23]. "
    [Show abstract] [Hide abstract] ABSTRACT: This work presents a systematic comparative study of analog/RF performance for underlap dual material gate (U-DMG) DG NMOSFET. In previous works, improved device performances have been achieved by use of high dielectric constant (k) spacer material. Although high-k spacers improve device performance, the intrinsic gain of the device reduces. For the analog circuits applications intrinsic gain is an important parameter. Hence, an optimized spacer material having dielectric constant, k = 7.5 has been used in this study and the gain is improved further by dual-material gate (DMG) technology. In this paper we have also studied the effect of gate material having different work function on the U-DMG DG NMOSFETs. This device exploits a step function type channel potential created by DMG for performance improvement. Different parameters such as the transconductance (gm), the gain per unit current (gm/Ids), the intrinsic gain (gmRo), the intrinsic capacitance, the intrinsic resistance, the transport delay and, the inductance of the device have been analyzed for analog and RF performance analysis. Analysis suggested that the average intrinsic gain, gm/Id and gm are increase by 22.988%, 16.10% and 27.871% respectively compared to the underlap single-material gate U-DG NMOSFET.
    Full-text · Article · Sep 2014
  • [Show abstract] [Hide abstract] ABSTRACT: In this paper, we analyze and optimize FinFETs with asymmetric drain spacer extension (ADSE) that introduces a gate underlap only on the drain side. We present a physics-based discussion of current-voltage relationships, short channel effects, and leakage and show the application of ADSE FinFETs in 6T static random access memory (SRAM) bit cell. By exploiting asymmetry in current, we show that it is possible to achieve improvement in both read and write stability for the 6T SRAM bit cell, along with reduction in cell leakage at the cost of negligible increase in access time and area. We also propose a general circuit-aware device optimization methodology for SRAM design. We use this methodology to optimize the underlap in ADSE FinFETs. Compared to conventional FinFETs, we achieve 57% reduction in leakage, 11% improvement in read static-noise margin, and 6% improvement in write margin, with 7% increase in access time and cell area.
    Article · Mar 2011
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