A CMOS multi-channel 10Gb/s transceiver

Conference PaperinDigest of Technical Papers - IEEE International Solid-State Circuits Conference · February 2003with10 Reads
DOI: 10.1109/ISSCC.2003.1234212 · Source: IEEE Xplore
Conference: Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International


    A quad 10Gb/s transceiver in 0.11μm CMOS communicates electric signals over balanced copper media. The transceiver uses a single 1.2V power supply and dissipates 415mW per channel. One PLL supplies a reference clock to two transmitter channels and two receiver channels. The transceiver contains analog front ends, clock recovery units, and 312MHz parallel interfaces.