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A 2.5-V CMOS Wideband Sigma-Delta Modulator
R. del Rio, E Medeiro, J.M. de la Rosa, B. PBrez-Verd6 and A. Rodriguez-Vbquez
Instimto de Micmelectrdnica de Sevilla - CNM-CSIC
Edif. CICA-CNM, Cmarfia s/n, 41012- Sevilla, SPAIN
Phone: +34 95 5056666, Fax: +34 95 5056686, e-mail: email@example.com
communication applications is presenfed It employs a 4fhth-order
cascade multi-bit orchitecfure that requires only 16 oversampling
rafio, and has been implemented using fully-di~erentialSCcircuirs
in a 0.25-pm CMOS technologv. Measurements show a dynamic
range of 84dB operating at 2.2MUs outpui rate, and 79dB af
4.4MWs. The wholeprotolype dissbates 65.8m Wfrom a 2.S-Vsupply.
- A high-performance XA modulator for wireline
The increasing demand for ever faster wireline
communication challenges mixed-signal designers to
integrate A/D and DIA interfaces featuring 12- to 16-bit for
signal bandwidths well in excess of lMHz [l]. In addition,
these specifications must be achieved in a low-voltage
scenario, making use of poor performance (and often badly
characterized) devices, which decreases the "analog speed" of
deep-submicron CMOS processes.
In this context, oversampled Sigma-Delta modulation
 is usually preferred to other AID conversion
techniques for its low-complexity analog circuitry and
robustness. However, the latter is absolutely true only if the
oversampling ratio ( M ) is high, which obviously cannot be
the case in high-speed communication. In fact, in spite of the
increasing potential speed of the new CMOS processes, the
trend is to decrease M, because of the concurrent increase of
the bandwidth specification.
In order to cope with oversampling ratios below 32,
high-order filtering andor multi-bit quantization must be used
-. As known, both strategies degrade the original
robustness of the highly oversampled low-order single-bit EA
conversion, which often
correctiodcalibration mechanisms and, definitely, to a more
careful analog design.
All these difficulties become harder the lower the supply
voltage. On the one hand, reducing the supply voltage hard
limits the achievable dynamic range (DR ). On the other, it
invalidates some popular circuit techniques, such as cascode
devices. In fact, only two wideband sigma-delta converters
obligates to resort to
have been reported so far in 2.5-V CMOS technologies,
namely  and [ll]. They are representative of the two main
architectural tendencies: a) high-order single-loop multi-bit
topologies [lO][ll]; and b) high-order cascade (MASH)
multi-bit topologies -, whose pros and cons are beyond
the scope of this paper. Although the modulator presented
here belongs to the latter category, it has a substantial
difference as compared to , that is explained in Section 2.
Section 3 describes its SC implementation and building
blocks. Last, experimental results are given in Section 4.
11. MODULATOR ARCHITECTURE
Fig.1 shows the block diagram of the architecture adopted.
The values of the integrator weights have been selected to
minimize the systematic loss of dynamic range due to
overloading issues, and to easy a 2.5-V supply SC
implementation. Instead of using multi-bit quantization in all
stages, like in  (thus sharing the DAC linearity bottle-neck
with the single-loop multi-bit modulators), multi-bit
quantization is used only in the last stage of a 3-stage 2-1-1
cascade. This dualquantization approach  - single-bit
quantizers are used in the remaining stages - considerably
Fig. 1.4th-order 2-1-1 cascade multi-bit U M
0-7803-7705-2/03/$17.00 02003 IEEE
simplifies the design of the circuihy, because the DAC
linearity is largely relaxed by the inherent attenuation of such
an error in these topologies . The price to pay is a larger
sensitivity to some circuit imperfections: namely, capacitor
ratio mismatching and finite amplifier DC-gain. All these
effects can be combined in the following approximate
equation for the in-band error power,
where the first term re resents the ideal quantization noise
contribution, with 0% = [A/(2B- 1)12/12
quantization error power of a B-bit quantizer with A full
scale. The second term accounts for the contribution of the
last-stage DAC non-linearity, where
an estimation of the error power induced by a DAC with INL
integral non-linearity referred to the full scale. Note that the
latter contribution is inversely proportional to M7, which
considerably attenuates its impact, even for low oversampling
ratios. This appealing feature allows us to use straight-forward
circuitry for implementing the last-stage ADC and DAC, with
neither correction nor calibration required.
The first term in parenthesis in (1) reflects the excess of
in-band error power due to integrator leakage (A,, is the
amplifier DC-gain), whereas the second term accounts for the
impact of mismatching in integrator weights, with ocr being
the sigma of capacitor, mismatching error. Note that the latter
errors are only 1st- and 2nd-order shaped (their in-band error
powers are inverselyiproportional to M3 and M5), so that
these extra error powers can ultimately limit the benefits of
multi-bit quantization in the last stage. This is illustrated in
Fig.2, where we show the resolution of the architecture used
vs. the multi-bit quantizer resolution B (with M being a
parameter), in the presence of typical values for A ,, , ocr , and
DAC INL. The thick solid line estimates the boundary
beyond which increasing B would not further improve DR.
= A* (INL) /2 is
lNLDAC = 0.4%FS
Fig. 2. X A h resolution vs. multi-bit resolution.
However, resolutions below this limit are enough to
significantly relax the circuit requirements with respect to
single-bit approaches, especially the integrator dynamics,
which often establish the feasibility limit in high-speed
converters. By including these dynamic requirements, an
estimation of the power consumption associated to the
different [ M , B ] pairs can be made, and used for optimum
architecture selection. Note that 14bit can be achieved with
M = 16, B = 3 , which establishes a good trade-off
between circuit complexity and clock frequency (70.4MHz
III. SWITCHED-CAPACITOR IMPLEMENTATION
Fig.3 shows the SC implementation of the ZAM in Fig.1.
Note the distribution of the integrator weights among the
input stages of the four SC integrators in order to save area.
The modulator operation is,controlled by two non-overlapped
clock-phases. In order to attenuate the signal-dependent clock
feedthrough, delayed versions of the two phases,
are also provided. This delay is incorporated only to the
falling edges of the clock-phases, while the rising edges are
synchronized in order to increase the effective time-slot for
the modulator operations 1121. The comparators and the ADC
are activated at the end of phase Q2, using qZd as a strobe
signal, to avoid any possible interference due to the transient
response of the integrators outputs at the beginning of the
sampling phase. The reference voltages have been set to
k1.5V (equivalent to Y, = 0.75 in the fully-differential
implementation) - enough to accommodate a full-scale DMT
The sampling capacitor of the first integrator, implemented
using MiM structures, has been set according to thermal noise
and integrator dynamics criteria. A lower value has been used
in the remainder integrators, whose contributions to the
in-band error power are gradually smaller. This also relaxes
the dynamic specifications for these integrators, and the same
applies to other specifications such as DC-gain. Although not
essential for performance, this relaxation significantly reduces
the power dissipation and hence increases the design
efficiency at the cost of designing more than one amplifier to
fit in with the assorted requirements. After deriving
appropriate values for the building block specifications
making use of the methodology in , two different opamps
one for the 1st and 2nd integrator: OPA, requiring 70dB
DC-gain, 315MHz gain-bandwidth product, 75OVlks
slew-rate, and 1.W output-swing), and
* another for the 3rd and 4th: OPB, requiring 56dB,
210MH2, 350V/ps, and 1.6V, respectively.
The electrical design was speeded up by the support of the
basic cell optimizer in .
As known, both the DC-gain/output swing, and
slew-rateloutput swing trade-offs get tighter in a 2.5-V
Fig. 3. SC implementation of the U M .
implementation. On the one hand, the supply voltage
shrinking forces to.use two-stage amplifiers to obtain high
DC-gain in a reduced output voltage range, resulting in highly
non-linear gain. On the other hand, high slew-rate requires
large device current and hence reduced voltage range. Thus,
there is a trade-off between transient response linearity and
output swing - the more evident the lower the supply voltage.
Both non-linear effects may generate distortion and have been
carefully controlled during the design phase following table
After exploring several alternatives for power optimization,
the two-stage topology in Fig.4 was selected for OPA in order
to fulfil its larger DC-gain specification. It uses a telescopic
1st-stage, and both Miller and Ahuja compensation . This
topology provides a robust control of the current in the second
stage, preserving a high output-swing. OPB is a single-stage
folded-cascode OTA - enough to achieve its lower DC-gain,
with reduced power dissipation. The common-mode feedback
nets are of dynamic type in order to further reduce power and
avoid voltage range problems.
Switches are also critical in a 2.5-V implementation
because the threshold voltage of the MOS devices is not
scaled down at the same rate as the supply voltage. So, the
CMOS transmission gates exhibit considerable on-resistance
Fig. 4. 2-stage 2-path compensated OTA.
on-resistance exhibits a highly non-linear characteristic that
may cause dynamic distortion
clock-bootstrapping increases complexity and leads to a less
robust design. This can be avoided by properly sizing the
CMOS switches and the input capacitor in the differential
sampling circuitry of the first integrator. Exhaustive electrical
simulation reveals that
maximum-frequency full-scale input sinewave. Thus,
clock-boosting is not required in the technology adopted.
Comparators at the end of the 1st and 2nd stage of the
cascade require a low resolution time, while uncertainty must
be kept bellow 20mV. A regenerative latch with a small
pre-amplifying stage was adopted. Given the low sensitivity
of this ZAM to the errors in the multi-bit stage, a simple 3-bit
flash ADC driving a poly-resistor ladder DAC was used, with
no calibratiodcorrection circuitry.
low-voltage technologies. Most importantly, the
THD< -95dB for a
IV. EXPERIMENTAL RESULTS
Fig.5 shows a microphotograph of the prototype fabricated
in a0.25-pm CMOS technology. It occupies 2.78mm2 without
pads and dissipates 65.8mW (including YO digital buffers)
from a 2.5-V supply. The modulator has been tested in a
4-layer PCB including intensive filtering and decoupling
strategies, as well as proper impedance termination to avoid
reflections in high-frequency signals. A standard digital tester
was used to provided a low-jitter external clock signal that is
buffered prior to the on-chip clock-phase generation. The
tester was also used to capture the 5 output bitstreams that
were later combined and processed by software. The input
signal consisted of a high-precision sinewave provided by a
fully-differential generator with
reference voltages are generated on-chip and their impedance
is kept small through both on- and off-chip decoupling
THD < -100dB. The
Fig. 5. Die microphotograph
strategies. Fig.6(a) shows a 65536-sample FIT of the
modulator output for a -3.8dBV@ 15OkHz input sinewave
sampled at 70.4MHz. The in-band noise is almost flat, and the
spurious level is small. However the noise floor is higher than
expected and changes with the sampling frequency, as shown
in Fig.6(b) for two values of the oversampling ratio. Note that
SFDR > 90dB
-1 50 1
Clock frequency (MHz)
Fig. 6. (a) Measured baseband spectrum, (b) In-band error
power vs. clock frequency.
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8 0 / - -
- - -
- - -
3 0 - ~ -
10 t - - ..
Fig. 7. SNDR v5. input level for M = 16. 32
around the nominal clock frequency the performance is
degraded due to the impact of the switching activity, specially
that in the YO buffers, which is distributed along the chip
through the pad ring. Significantly, the in-band error power
decreases with temperature, reaching a minimum at 1 10°C.
This is explained by the slowdown of the digital circuitry
caused by the temperature increase, which attenuates the
high-frequency components of the switching signals.
Fig.7 shows the signal-to-(noise+distortion)-ratio SNDR
as a function of the input level (OdB = reference voltage). For
M = 16, the DR measured is 79dB (12.8bit) with a SNDR
peak of 74dB; for M :
32, DR = 84dB (13.7bit) and
SNDR peak = 8ldB. With the performance measured at
M = 16, the low consumption of this prototype yields 2.lpJ
for the Power/(Zbil. Nyquist rate) figure-of-merit (FOM),
which is the third smallest value reported for high-frequency
XA modulators. only behind  (5-V 0Scm CMOS,
FOM = 1.3pJ) and 
FOM = 1.14pJ).
This work has been supported by the CEE (ESPRIT IST
Project UM1-34283mAMES-2) and the Spanish MCyT and
the ERDF (Project TIC2001-0929/ADAVERE)
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