A Methodology for Accurate Modeling of Energy Dissipation in Array Structures
Mahesh N. Mamidipaka
Center for Embedded Computer Systems
University of California, Irvine, CA 92697
Nikil D. Dutt Kamal S. Khouri
Arch. and Systems Platforms
Motorola Inc., Austin, TX 78729
There is an increasing need for obtaining a reasonably ac-
curate estimate of energy dissipation in SoC designs. Array
structures have a significant contribution to the total system
level energy consumption. In this paper, we propose a new
methodology to develop analytical models for accurately es-
timating energy dissipation in array structures. The method-
ology is based on the characterization of arrays for energy as
a function of micro-architecture level inputs. The coefficients
of the function are extracted using circuit level simulations.
We applythe proposed methodologyto developenergymodels
for three different array structures used in the Motorola e5001
processor core. The models are validated by comparing them
against post-layoutSPICE simulation. The energy models are
seen to be highly accurate with an error margin of less than
8%. While the experiments are specific to the e500 processor
core based array structures, the methodology is generic and
can be used to develop energy models for array structures of
any SOC design.
Energy dissipation has become critical design factor in
SOC designs. Until recently, energy dissipation was consid-
ered important only to portable systems as it determines the
battery lifetime. However, there is a growing concern on en-
ergy dissipation in application domains such as high-speed
desktopand networkprocessing. In these systems, decreasing
feature and die size and higher clock rates significantly in-
crease the power density, thereby affecting system reliability
higher cooling system costs increases the over all cost of the
system. In the network processor domain, heat removal sys-
tems have a fixed capacity, limiting the number of processors
that can be placed in the server/switch farm. This demands
an early and reasonably accurate estimate of the energy dissi-
pated in a processor for a given application.
Traditionally power dissipation in micro-architectural
blocks is estimated using gate level simulations for combi-
national logic and transistor level simulations for array struc-
tures. However, because of their long simulation times, these
1e500 is the Motorola processor core that is compliant with the PowerPC
Book E architecture
techniques are not practical for power estimation at an ap-
plication level. To overcome this, researchers have focussed
on developing analytical models as a function of micro-
architecture level inputs. Estimation of energy dissipation in
a processor at an application level helps in: 1. Rapid design
space exploration by evaluating different power-performance
tradeoffs for an application. 2. Possible elimination of hot-
spots by determining the power distribution across modules
for a given processor configuration and a given application.
3. Optimizing the software for reduction in power dissipation
 for a given configuration
Array structures are an important class of modules in cur-
rent day micro-processors. Not only do they consume signif-
icant portion of the die area, but also have a major contribu-
tion to the overall power dissipation in processors. It can be
notedthat the arraystructures(viz. registerfiles, branchtarget
buffer, reservation stations, tag arrays, caches) consume up to
70% of the total chip power . Also, it has been shown that
caches alone consume up to 40% of total power . Existing
models in the literature have focussed on estimating energy
dissipation in array structures based on conventional style of
implementation. The accuracyof these models is limited con-
sidering the wide variety of possible implementation styles
in array structures. In this paper, we propose a methodology
for modeling energydissipation in existing array structure de-
signs with an emphasis on accuracy. We show that for differ-
ent implementations of array sub-blocks, the energy dissipa-
tion can be characterized as a function of primary inputs and
outputs. The coefficients of the function are then extracted
using accurate circuit level simulations. The methodology
yields analytical models which take micro-architecture level
inputs(write data, write address, read data, read address etc.)
as parameters. The methodology is generic and can used for
modeling arrays belonging to any processor/system designs
because of their similar inherent structure. To the best of our
knowledge, this is the first work which proposes a generic
methodology for modeling energy dissipation in array struc-
tures over wide variety of possible implementation styles.
The paper is organized as follows. The related work is
discussed in Section 2. Section 3 presents an overview of
different array structures used in current SOC designs with
regard to their operations and their implementation details.
The methodologyused for extractingthe energymodels is de-
0-7695-1868-0/03/$17.00 (C) 2003 IEEE
5.3 Conventional memory array
This array structure has 64 rows and 2 sets of 40 columns.
The design supports 20-bit read and write operations. The ap-
propriate columns for read and write operations are selected
through logic implemented in control circuitry. The control
logic also controls the signals and clocks to column multi-
plexers, precharging logic, and differential sense-amplifiers.
The row decoder is implemented with static CMOS logic and
hence there would be energy dissipation in the decoder only
when there is change in row address. The reads and writes to
the memory locations are implemented through double ended
bit lines with a single access port. The main features of this
array structure are indicated below:
• Static CMOS based row decoder
• 1 access port (same port for both reads and writes)
• Double ended precharge based bitlines with reads using
The schematic of the memory cell in this conventional ar-
ray structure is shown in Figure 6. The energy dissipation
models based on simulations for read and write operationsare
shown in Equation 5 and 6 respectively. It should be noted
that unlike simple register file or the GPR the energy dissipa-
tion on bitlines is constant for both reads and writes because
of the double ended precharge based implementation. Also
Equation 5 implies that the energy dissipation due to a read
operation in a conventional array structure is constant if there
is change in the row address. Table 3 shows the percentage
of the total energy dissipation for each sub-circuit for reads
and writes for this design and the percentage error compared
to actual measurements. Note that the energy dissipation on
wordline is included in the decoder energy. The simulation
based estimates are highly accurate and are seen to have less
than 1% error margin for both reads and writes. As was men-
tioned in the previous section, the dominant error in estima-
tion of memory cell power for a write operation is because
of the approximation in transition activity because of a data
Figure 6. Schematic of the Memory Cell in Con-
ventional Array Structure
Erd= EDec+ EBitlines+SA+ ECntrl+ ECon
= E1∗ (# of row addr. changes) + E2+ E3+ E4
= K1∗ Nrow chg+ K2
Ewrt= EDec+ EBitlines+ ECntrl+ EMemWrt+ ECon
= E1∗ (# row addr. changes) + E2+ E3∗ (# trans on
col. addr.) + E4∗ (# mem trans. due to wrt) + E5
= K1+ K2∗ Nrow chg+ K3∗ Ncol trans
+K4∗ Nmem trans (6)
Table 3. Energy Distribution and Accuracy for a
Conventional Array Structure
6 Conclusions and Future Work
In this paper, we proposed a methodologyto generate sim-
ulation based analytical models as a function of primary input
and outputs. These models can be used for accurate proces-
sor power estimation at an application level and for micro-
architecture level design space exploration. Experimental re-
sults show that the models are highly accurate with an error
margin of less than 8%. The simulation times for extracting
the power models is in the order of few hours. However, this
is only a one time effort needed for extracting the analytical
models. Althoughthe experimentswere doneonthe Motorola
e500 processor core based array structures, the methodology
is generic and is applicable to array structures of any system
design. The energy models generated using this methodology
cific technology. Future work will involve developing models
Also, we plan to develop a characterization methodology for
other micro-architectural components.
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