Conference Paper

Automatic generation of digital cell libraries

Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
DOI: 10.1109/SBCCI.2002.1137669 Conference: Integrated Circuits and Systems Design, 2002. Proceedings. 15th Symposium on
Source: IEEE Xplore


This paper presents cell design flow - CDF, a tool for automatic generation of digital cell libraries. It is able to synthesize physical layouts of logic cells from truth table descriptions or Boolean equations. The tool is also able to generate a complete set of cells according to boundary conditions, such as the maximum number of cell inputs and the maximum number of serial transistors. The libraries provided by CDF are compatible to professional IC design environments, like Cadence and Mentor Graphics.

Download full-text


Available from: André Inácio Reis
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper proposes a protocol for data exchange to allow the communication of specialized tools with Eletronic Design Automation (EDA) frameworks. The BICO (BasIc type COnversor) protocol is based on SOAP, a Web-Service technology. The aim of BICO is to support interoperability, integration and cooperation between scripting and general-purpose languages, with minimum programming effort. The BICO protocol is able to automatically encode and decode data structures used as parameters of requests and replies of services implemented in different languages. Beyond the coder and decoder (CODEC) itself, a helper tool for the creation of the definitions needed by the protocol and some basic communication mechanisms is provided. Case studies are used to demonstrate the integration of specialized tools with commercial frameworks. The proposed protocol achieves interoperability with a simple and easy-to-learn mechanism and yet is very efficient for the purposes it was designed. The proposed integration method has learning costs affordable by university and small developers that want their tools linked to commercial environments or frameworks.
    No preview · Conference Paper · Jan 2005
  • [Show abstract] [Hide abstract]
    ABSTRACT: This work evaluates different CMOS logic families for asynchronous circuit design. The comparison is focused on self-timed circuit using four-phase protocol and dual-rail encoding in functional blocks with completion detection. Seven single-output and three multiple-output logic families were compared through electrical simulations taking into account both 0.13mum and 90nm CMOS technologies
    No preview · Conference Paper · Jan 2006
  • [Show abstract] [Hide abstract]
    ABSTRACT: Current standard cell libraries are not well equipped to take full advantage of advances in deep submicron technology by implementing functions as complex gates. In a technology process capable of supporting five serial MOS devices, 425,803 unique complex gates may be created-clearly much higher than what is currently available in today's cell libraries. A richer cell library allows the technology mapper more freedom to better select matches to reduce area, delay and power consumption. This paper proposes a novel algorithm for mapping an input netlist to a library of virtual cells to select an architecture which minimizes the design area. Simulation results show an average of 64.93% reduction in transistor count, 51.72% reduction in circuit area at the cost of 5.72% increase in delay by applying this algorithm to standard benchmark circuits compared to results obtained from Synopsys Design Compiler with high map effort for delay minimization.
    No preview · Article · Jun 2009
Show more