No full-text available
To read the full-text of this research,
you can request a copy directly from the authors.
Single-chip CMOS image sensor for mobile applications
Abstract
Not Available
... It has GPRS connectivity and can be used in vehicle surveillance system. In [25], a singlechip image sensor for mobile applications realized in a standard 0.35 um CMOS technology is presented. In [26], a solution to reduce the computational complexity of image processing by performing some low-level computations on the sensor focal plane is presented. ...
A design of a novel bridge is proposed to interface digital-video-port (DVP) compatible image sensors with popular microcontrollers. Most commercially available CMOS image sensors send image data at high speed and in a row-by-row fashion. On the other hand, commercial microcontrollers run at relatively slower speed, and many embedded system applications need random access of pixel values. Moreover, commercial microcontrollers may not have sufficient internal memory to store a complete image of high resolution. The proposed bridge addresses these problems and provides an easy-to-use and compact way to interface image sensors with microcontrollers. The proposed design is verified in FPGA and later implemented using CMOS 0.18 um Artisan library cells. The design costs 4,735 gates and 0.12 mm2 silicon area. The synthesis results show that the bridge can support a data rate up to 254 megasamples/sec. Its applications may include pattern recognition, robotic vision, tracking system, and medical imaging.
... In summary, each new technology process offers (1) to integrate more processing functions in a given silicon area, or (2) to integrate the same functionalities in a smaller silicon area. This can benefit the quality of imaging in terms of resolution, noise, for example, by integrating specific processing functions such as correlated double sampling [13], antiblooming [14], high dynamic range [15], and even all basic camera functions (color processing functions, color correction, white balance adjustment, gamma correction) onto the same camera-on-chip [16]. Furthermore, employing a processing element per pixel offers the ability to exploit the high speed imaging capabilities of the CMOS technology by achieving massively parallel computations [17] [18] [19] [20]. ...
A high-speed analog VLSI image acquisition and low-level image processing system are presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel operators are implemented on the circuit. Each pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A 64×64 pixel proof-of-concept chip was fabricated in a 0.35 μm standard CMOS process, with a pixel size of 35 μm × 35 μm. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. The chip can capture raw images up to 10 000 frames per second and runs low-level image processing at a framerate of 2 000 to 5 000 frames per second.
An image is partitioned into non-overlapping blocks fer JPEG compression. A scan order converter is placed before the JPEG encoder to provide blocks from the pixels in raster scan order. In general, its architecture requires two line memories for storing eight lines separately to allow the concurrent memory access by both the camera and JPEG processors. Although such architecture is simple to be implemented, it can be inefficient due to too excessive memory requirement as the image resolution increases. However, no deterministic addressing equation has been developed for scan conversion. In this paper, an effective memory addressing algorithm is proposed that can be devised only by adders and subtracters to implement a scan converter based on the single line memory.
A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper. The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a three-phase column-parallel circuit based on two floating gate inverters and switched-capacitor network. The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step. A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step, which can reduce the clock step from 2n
to 2(n/2+1). The floating gate inverters are implemented to reduce the power consumption. Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter, which can equalize the coupling path in three phases of the proposed circuit. This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18 μm process. Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10 MHz. The power consumption of this circuit is less than 36.5 μW with a 3.3 V power supply. The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.
A high speed analog VLSI image acquisition and low-level image processing system is presented. The architecture of the chip
is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling
the computation of programmable mask-based image processing in each pixel. Each pixel include a photodiode, an amplifier,
two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A 64×64 pixel proof-of-concept
chip was fabricated in a 0.35μm standard CMOS process, with a pixel size of 35μm×35μm. The chip can capture raw images
up to 10,000 fps and runs low-level image processing at a framerate of 2,000–5,000 fps.
KeywordsCMOS image sensor-Parallel architecture-SIMD-High-speed image processing-Analog arithmetic unit
The role of CMOS Image Sensors since their birth around the 1960s, has been changing a lot. Unlike the past, current CMOS Image Sensors are becoming competitive with regard to Charged Couple Device (CCD) technology. They offer many advantages with respect to CCD, such as lower power consumption, lower voltage operation, on-chip functionality and lower cost. Nevertheless, they are still too noisy and less sensitive than CCDs.Noise and sensitivity are the key-factors to compete with industrial and scientific CCDs. It must be pointed out also that there are several kinds of CMOS Image sensors, each of them to satisfy the huge demand in different areas, such as Digital photography, industrial vision, medical and space applications, electrostatic sensing, automotive, instrumentation and 3D vision systems.In the wake of that, a lot of research has been carried out, focusing on problems to be solved such as sensitivity, noise, power consumption, voltage operation, speed imaging and dynamic range. In this paper, CMOS Image Sensors are reviewed, providing information on the latest advances achieved, their applications, the new challenges and their limitations. In conclusion, the State-of-the-art of CMOS Image Sensors.
This paper surveys in a systematic way recent advances in single-sensor imaging. In particular, the most distinctive elements of a single-sensor imaging pipeline, such as color filter array configurations, image interpolation solutions, and picture storage approaches are reviewed and commented upon. New perspectives in the field are proposed, suggesting that the demand for consumer digital camera solutions and digital color imaging applications will continue.
A 1/3-inch, 800<sup>H</sup> x 600<sup>v</sup> pixels, 5.6 x 5.6 mum<sup>2</sup> color CMOS image sensor with three photocurrent integrations in pixel photodiodes, pixel lateral overflow capacitors and column capacitors fabricated in a 0.18 mum 2P3M CMOS technology has been reported. The image sensor operates using photodiode integrations and lateral overflow integrations in low light condition and achieves a wide dynamic range (DR) performance of around 100 dB in its one exposure. The wide DR performance in one exposure makes high S/N ratios at the signal switching points in the multiple exposures. The CMOS image sensor also operates using the column capacitor integration in very bright light condition. In the column capacitor integration, the photocurrents generated at the photodiodes are directly integrated at the column capacitors in each column line. The combination of two exposures using the photodiode integrations and the lateral overflow integrations and one exposure using the column capacitors leads to the whole linear photo-electric conversion responses from low light to very bright light region. The fabricated image sensor achieves a high S/N ratio, a fully linear response and over 180 dB DR in the incident light ranging from about 1.4 x 10<sup>-2</sup> lx to about 2.4 x 10<sup>7</sup> lx.
This paper proposes an architecture of the wireless endoscopy system for the diagnoses of whole human digestive tract and real-time endoscopic image monitoring. The low-power digital IC design inside the wireless endoscopic capsule is discussed in detail. A very large scale integration (VLSI) architecture of three-stage clock management is applied, which can save 46% power inside the capsule compared with the design without such a low-power design. A stoppable ring crystal oscillator with minimal overhead is used in the sleep mode, which results in about 60-muW system power dissipation in sleep mode. A new image compression algorithm based on Bayer image format and its corresponding VLSI architecture are both proposed for low-power, high-data volume. Thus, 8 frames per second with 320*288 pixels can be transmitted with 2 Mb/s. The digital IC design also assures that the capsule has many flexible and useful functions for clinical application. The digital circuits were verified on field-programmable gate arrays and have been implemented in 0.18-mum CMOS process with 6.2 mW
ResearchGate has not been able to resolve any references for this publication.