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Some techniques for performance improvements of DRAMs in multimediaapplications
Abstract
DRAM memory performance is critical, factor in many multimedia applications. Some techniques, which improve DRAM memory performance, are proposed in this paper. These are, first, combined strategies of opening and closing DRAM pages, and second, address remapping in DRAM memory referencing. Simulations we have done showed some improvements in latency of memory references. Implied requirements on DRAM controller are also discussed
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This document describes release 2.0 of the SimpleScalar tool set, a suite of free, publicly available simulation tools that offer both detailed and high-performance simulation of modern microprocessors. The new release offers more tools and capabilities, precompiled binaries, cleaner interfaces, better documentation, easier installation, improved portability, and higher performance. This paper contains a complete description of the tool set, including retrieval and installation instructions, a description of how to use the tools, a description of the target SimpleScalar architecture, and many details about the internals of the tools and how to customize them. With this guide, the tool set can be brought up and generating results in under an hour (on supported platforms).
In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-based performance study of a representative group, each evaluated in a small system organization. These small-system organizations correspond to workstation-class computers and use on the order of IO DRAM chips. The study covers Fast Page Mode, Extended Data Out, Synchronous, Enhanced Synchronous, Synchronous Link, Rambus, and Direct Rambus designs. Our simulations reveal several things: (a) current advanced DRAM technologies are attacking the memory bandwidth problem but not the latency problem; (b) bus transmission speed will soon become a primary factor limiting memory-system performance; (c) the post-12 address stream still contains significant locality, though it varies from application to application; and (d) as we move to wider buses, row access time becomes more prominent, making it important to investigate techniques to exploit the available locality to decrease access time
This paper describes a performance examination of the DDR2 DRAM architecture and the proposed cache-enhanced variants. These preliminary studies are based upon ongoing collaboration between the authors and the Joint Electronic Device Engineering Council (JEDEC) Low Latency DRAM Working Group, a working group within the JEDEC 42.3 Future DRAM Task Group. This Task Group is responsible for developing the DDR2 standard. The goal of the Low Latency DRAM Working Group is the creation of a single cache-enhanced (i.e. low-latency) architecture based upon this same interface. There are a number of proposals for reducing the average access time of DRAM devices, most of which involve the addition of SRAM to the DRAM device. As DDR2 is viewed as a future standard, these proposals are frequently applied to a DDR2 interface device. For the same reasons it is advantageous to have a single DDR2 specification, it is similarly beneficial to have a single lowlatency specification. The authors are involv...
DSP and multimedia applications can be very demanding of memory
parameters. Typical requirements of memory parameters in such
applications are quoted in the paper. Based on these requirements, two
types of contemporary DRAM memories, Rambus DRAM and SLDRAM, are
considered as candidate memories in such systems. The results given in
the paper show that these memories can satisfy very demanding
requirements of DSP and multimedia applications
Ocena performansi savremenl DRAM meinorija " , Z l ~ ~ i k rurlova XLfV korz$erencijc ETRAN-ci, sveska 111, str
- V Stankovic
- N Milenkovic
V. Stankovic, N. Milenkovic, " Ocena performansi savremenl DRAM meinorija ", Z l ~ ~ i k rurlova XLfV korz$erencijc ETRAN-ci, sveska 111, str. 103-106.