Zynq-7000 FPGA-in-the-loop implementation of fractional-order PID controllers using a hybrid fixed-point and floating-point approach

Abstract

Implementing FPGA-based fractional-order controllers in real-time applications can be challenging due to their memory dependencies. These dependencies require high-order integers, leading to several design complications. Issues such as large design sizes, space exploration, and difficulty creating configurable hardware can affect resource utilization, power consumption, and accuracy. Therefore, this paper presents the implementation of a family of fractional-order PID controllers on the Zynq-7000 FPGA using the Tustin approximation technique, which addresses the memory dependency issue in real-time applications. A hybrid approach combining fixed and floating-point methods enhances computational efficiency, reducing resource utilization alongside greater precision and accuracy. The controllers evaluated include PID, PI-PD1, PI-PD2, PIDD, PIα-PD1, PIα-PD2, PI-PDβ1, PI-PDβ2, PIα-PDβ1, PIα-PDβ2, PIαDβ, and PIDDβ. These controllers are implemented on three different plants, allowing for a comparison between fractional-order and traditional controllers. The design utilizes the FPGA-in-the-Loop (FIL) feature for real-time validation and performance evaluation through MATLAB/Simulink and Xilinx Vivado. In Plant 1, the PIα-PD2 controller exhibits the least overshoot and the shortest rise time with power consumption from Xilinx of 0.3W. Similarly, in plant 2, all the fractional-order controllers demonstrate less overshoot and quicker settling time than the integer-order controllers with a power consumption of 0.3W. Finally, in plant 3, the fractional-order controller achieves significantly less overshoot and a much shorter rise time than traditional controllers, with power consumption ranging from 3W to 4W. Overall, the performance of Zynq-7000 FPGA-based fractional-order controllers shows improvements in step response characteristics, resource utilization, and power consumption compared to the traditional controllers.

Full text

Eng. Res. Express 7(2025)025341 https://doi.org/10.1088/2631-8695/add4ca
PAPER
Zynq-7000 FPGA-in-the-loop implementation of fractional-order PID
controllers using a hybrid fixed-point and floating-point approach
Aijaz Ali
1
, Kishore Bingi
1
, Rosdiazli Ibrahim
1
, Lalit Bansal
2
and Madiah Omar
3
1
Department of Electrical and Electronics Engineering, Universiti Teknologi PETRONAS, Seri Iskandar, Malaysia
2
Central Scientific Instruments Organization (CSIR), Sector 30, 160030, Chandigarh, India
3
Department of Chemical Engineering, Universiti Teknologi PETRONAS, Seri Iskandar, Malaysia
E-mail: bingi.kishore@utp.edu.my
Keywords: Zynq-7000 FPGA, fixed-point, floating-point, fractional-order controllers, Xilinx Vivado, FPGA-in-the-Loop, resource
utilization
Abstract
Implementing FPGA-based fractional-order controllers in real-time applications can be challenging
due to their memory dependencies. These dependencies require high-order integers, leading to several
design complications. Issues such as large design sizes, space exploration, and difficulty creating
configurable hardware can affect resource utilization, power consumption, and accuracy. Therefore,
this paper presents the implementation of a family of fractional-order PID controllers on the Zynq-
7000 FPGA using the Tustin approximation technique, which addresses the memory dependency
issue in real-time applications. A hybrid approach combining fixed and floating-point methods
enhances computational efficiency, reducing resource utilization alongside greater precision and
accuracy. The controllers evaluated include PID, PI-PD1, PI-PD2, PIDD, PI
α
-PD1, PI
α
-PD2,
PI-PD
β
1, PI-PD
β
2, PI
α
-PD
β
1, PI
α
-PD
β
2, PI
α
D
β
, and PIDD
β
. These controllers are implemented on
three different plants, allowing for a comparison between fractional-order and traditional controllers.
The design utilizes the FPGA-in-the-Loop (FIL)feature for real-time validation and performance
evaluation through MATLAB/Simulink and Xilinx Vivado. In Plant 1, the PI
α
-PD2 controller exhibits
the least overshoot and the shortest rise time with power consumption from Xilinx of 0.3W. Similarly,
in plant 2, all the fractional-order controllers demonstrate less overshoot and quicker settling time
than the integer-order controllers with a power consumption of 0.3W. Finally, in plant 3, the
fractional-order controller achieves significantly less overshoot and a much shorter rise time than
traditional controllers, with power consumption ranging from 3W to 4W. Overall, the performance of
Zynq-7000 FPGA-based fractional-order controllers shows improvements in step response character-
istics, resource utilization, and power consumption compared to the traditional controllers.
1. Introduction
Fractional-order controllers, such as the PI
α
D
β
controllers, have gained significant attention in recent years due
to their improved efficiency compared to conventional PID controllers, particularly for managing complicated
and nonlinear systems. Unlike traditional PID controllers, which rely on integer-order derivatives and integrals,
PI
α
D
β
controllers introduce two additional tuning parameters, the order of integration and the order of
differentiation, which can take non-integer fractional values. This added flexibility allows PI
α
D
β
to enhance the
control performance in many real-world applications such as complex dynamics, improved robustness, and
flexibility, and it will enhance the performance in time-delay systems. The advantages of these fractional-order
controllers make them suitable for applications that require robust and adaptive control strategies. When
selecting PI
α
D
β
controllers for control applications, the focus is on their potential to enhance closed-loop
performance, system robustness, and their superiority over conventional PID controllers [1]. With more
parameters than traditional controllers, fractional controllers can meet additional criteria, thus improving
overall system performance and increasing resilience against plant uncertainties, including variations in gain
RECEIVED
17 March 2025
REVISED
30 April 2025
ACCEPTED FOR PUBLICATION
6 May 2025
PUBLISHED
14 May 2025
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