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A 1.0 Gb/s BiCMOS multi-channel optical interface transmitter andreceiver chip set for high resolution digital displays
Abstract
In this paper, a 1.0 Gb/s multi-channel optical interface transmitter (Tx) and receiver (Rx) chip set is presented. For a high resolution liquid crystal display (LCD) operating up to SXGA (1280×1024) pixels) grade, we present a high speed serial digital video I/O scheme with low EMI, skew-tolerant and long transmission distance. The interface chip set has a data recovery system with ±1 bit skew compensation and a 8B9B encoding/9B8B decoding for dc balancing. The analog front ends of the optical interface such as laser driver in Tx and PD current detector in Rx are fully integrated in the chip set. The Tx consists of an encoder, a pipelined high speed serializer, and a vertical cavity surface emitting laser (VCSEL) driver. The Rx consists of a transimpedance amplifier for PD input, a deserializer, and a decoder for each channel. Fully integrated low jitter PLLs are implemented for clocking in the chip set. With a single 2.5 V supply operating at 1.0 Gb/s, the power consumption of the Tx is 150 mW and that of the Rx is 230 mW. They were implemented in a 0.5 um, 3-metal BiCMOS process and occupy an active area of 3,170*3,440 mm<sup>2 </sup> each
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This paper describes a byte-oriented binary transmission code and its implementation. This code is particularly well suited for high-speed local area networks and similar data links, where the information format consists of packets, variable in length, from about a dozen up to several hundred 8-bit bytes. The proposed transmission code translates each source byte into a constrained 10-bit binary sequence which has excellent performance parameters near the theoretical limits for 8B/10B codes. The maximum run length is 5 and the maximum digital sum variation is 6. A single error in the encoded bits can, at most, generate an error burst of length 5 in the decoded domain. A very simple implementation of the code has been accomplished by partitioning the coder into 5B/6B and 3B/4B subordinate coders.
A BiCMOS circuit for serial data communication is presented. The
chip has phase-locked loops for transmit frequency synthesis and receive
clock recovery, serial-to-parallel and parallel-to-serial converters,
and encode and decode functions. Since this is a mixed-analog/digital
design, and the transmitter and receiver operate asynchronously, many
techniques are used to decrease noise coupling. A 1.2 μm BiCMOS
process allows operation at speeds of 300 MHz along with this high level
of system integration, and the chip consumes less than 1 W from a single
5 V supply