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A 206–220-GHz Compact Fundamental Oscillator With up to 7-dBm Output Power and 7.4% Peak DC-to-RF Efficiency in a 130-nm SiGe Technology

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This letter presents a 206.5–220.5-GHz fundamental differential Colpitts oscillator in a cascode topology implemented in a 130-nm SiGe HBT technology with f t / f max of 350/450 GHz. Base inductors at the common-base (CB) stages are used to provide an inductive load at the output of the common-emitter (CE) stage, hence, boosting the output power by 27%. The resonant tank is embedded straight on top of the devices, reducing layout parasitics and resulting in a compact and efficient oscillator core layout. The oscillator provides a peak output power of 7 dBm at 208 GHz, 7.4% peak dc-to-RF efficiency at 220 GHz, and 6.55% tuning range (TR). At peak efficiency, the oscillator delivers an output power of 5.7 dBm with 50-mW dc power consumption and a phase noise (PN) of -90.2/-110 dBc/Hz at 1-/10-MHz offset, respectively. To the best of the authors’ knowledge, the presented oscillator has the best PN figure-of-merit (FoM) of -182.1 dBc/Hz at 1-MHz offset in a SiGe/CMOS technology above 200 GHz. It occupies a total area of 0.086 mm2, including the RF pad, and an ultracompact core size of 0.0049 mm2.
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IEEE MICROWAVE AND WIRELESS TECHNOLOGY LETTERS 1
A 206–220-GHz Compact Fundamental Oscillator
With up to 7-dBm Output Power and 7.4% Peak
DC-to-RF Efficiency in a 130-nm SiGe Technology
Arjith Chandra Prabhu , Graduate Student Member, IEEE, Janusz Grzyb , Marcel Andree , Member, IEEE,
Holger Rücker , and Ullrich R. Pfeiffer , Fellow, IEEE
Abstract This letter presents a 206.5–220.5-GHz fundamental
differential Colpitts oscillator in a cascode topology implemented
in a 130-nm SiGe HBT technology with ft/fmax of 350/450 GHz.
Base inductors at the common-base (CB) stages are used to
provide an inductive load at the output of the common-emitter
(CE) stage, hence, boosting the output power by 27%. The
resonant tank is embedded straight on top of the devices,
reducing layout parasitics and resulting in a compact and
efficient oscillator core layout. The oscillator provides a peak
output power of 7 dBm at 208 GHz, 7.4% peak dc-to-RF
efficiency at 220 GHz, and 6.55% tuning range (TR). At peak
efficiency, the oscillator delivers an output power of 5.7 dBm
with 50-mW dc power consumption and a phase noise (PN) of
90.2/110 dBc/Hz at 1-/10-MHz offset, respectively. To the best
of the authors’ knowledge, the presented oscillator has the best
PN figure-of-merit (FoM) of 182.1 dBc/Hz at 1-MHz offset in a
SiGe/CMOS technology above 200 GHz. It occupies a total area
of 0.086 mm2, including the RF pad, and an ultracompact core
size of 0.0049 mm2.
Index Terms Colpitts, dc-to-RF efficiency, frequency gener-
ators, fundamental oscillator, mm-Wave, output power, phase
noise (PN), PN figure-of-merit (FoM), power boosting, SiGe,
ultracompact.
I. INTRO DUC TIO N
FREQUENCY generators at mm-Wave frequencies play a
crucial role in high data-rate wireless communication [1],
[2],[3], radar systems [4],[5],[6], high-resolution terahertz
(THz) imaging systems [7],[8], and spectroscopy [9],[10].
In coherent systems applied in laser holography [11] and
high-resolution radar imaging [5],[12], not only amplitude but
also phase information are extracted, allowing distance mea-
surements with an accuracy in the µm range [13]. Extracting
accurate phase information typically requires locked sources
based on a phase-locked loop (PLL) feedback system. How-
ever, implementing a PLL at frequencies beyond 200-GHz
poses a challenge due to the lack of frequency dividers at these
frequencies. Another approach for signal locking is based on
Received 31 January 2025; accepted 19 February 2025. This work was
supported by the European Research Council (ERC) through the European
Union’s Horizon 2020 Research and Innovation Programme under Grant
101019972. (Corresponding author: Arjith Chandra Prabhu.)
Arjith Chandra Prabhu, Janusz Grzyb, Marcel Andree, and
Ullrich R. Pfeiffer are with the Institute of High-Frequency and
Communication Technology, University of Wuppertal, 42119 Wuppertal,
Germany (e-mail: chandra@uni-wuppertal.de).
Holger Rücker is with the IHP—Leibniz-Institut für Innovative
Mikroelektronik, 15236 Frankfurt (Oder), Germany.
Digital Object Identifier 10.1109/LMWT.2025.3546162
Fig. 1. Comparison of SOTA efficiency and output power of oscillators in
SiGe (blue) and CMOS (red) technologies operating from 180 to 300 GHz.
the injection locking method [14],[15],[16],[17] which tends
to be area-consuming or inefficient. An alternative approach
for high-resolution 3-D imaging is based on light-field ray-
tracing [18] utilizing multipixel focal plane arrays (FPAs) of
incoherent sources resulting in a compact and efficient imaging
system.
High power frequency sources beyond fmax/2 become
challenging due to the transistor degraded performance and
increased back-end losses. Typically, such sources are imple-
mented using an oscillator at lower frequencies followed by
a frequency multiplier chain [19],[20],[21]. Here, peak
output powers of 9.6 dBm at 270 GHz occupying an area of
0.92 mm2with 1.38% efficiency [19] and 8 dBm at 240 GHz
occupying an area of 0.28 mm2with 1.47% efficiency [21]
are reported. Nevertheless, due to the high area and low
efficiency, such multiplier chains are unsuitable as sources
in large-scale FPAs for THz light-field applications. A good
alternative is different oscillator topologies, subdivided into
harmonic, push–push/triple-push, and fundamental oscillators
that are generally compact and efficient at the cost of output
power. In more detail, an efficiency of up to 15.3% and
6.5-dBm output power at 195 GHz [22] that drops to 12.3%
with 5.17-dBm output power at 215 GHz [23], 2.76% with
2.74-dBm output power at 293 GHz [24] are reported,
while in [25] a 301-GHz push–push oscillator [26] with an
efficiency of 2.8% and 2.85-dBm output power is presented.
The corresponding state-of-the-art (SOTA) trend in dc-to-RF
efficiency and output power of oscillators in SiGe and CMOS
technologies beyond 200 GHz is shown in Fig. 1.
This letter presents an efficient and compact 206–220-GHz
fundamental differential Colpitts oscillator in a 130-nm SiGe
HBT technology, which utilizes a 10 pH base inductor to boost
the output power by 27% by providing an inductive load to the
output of the common-emitter (CE) device. The innovative lay-
out reduces the parasitic effects by implementing the resonant
inductor and capacitor directly above the transistors resulting
in a compact oscillator core. The oscillator delivers the highest
© 2025 The Authors. This work is licensed under a Creative Commons Attribution 4.0 License.
For more information, see https://creativecommons.org/licenses/by/4.0/
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2 IEEE MICROWAVE AND WIRELESS TECHNOLOGY LETTERS
Fig. 2. Schematic of the ×4 ( Ae=4×0.07 µm×0.9 µm) fundamental
differential Colpitts oscillator with output matching and biasing networks.
output power compared to the SOTA above 200 GHz with
values up to 7 dBm, a maximum peak efficiency of 7.4%,
and occupies a total area of 0.086 mm2. The corresponding
efficiency and power are well above the trend line shown in
Fig. 1.
II. CIR CUI T DESIGN
The fundamental oscillator is designed in a 130-nm SiGe
BiCMOS HBT technology with a ft/fmax of 350/450 GHz
offering a 12-µm-thick seven-metal aluminum back-end with
two thick top-metal layers [43] and complying to the standard
DRC rules of the technology. All inductors and transmission
lines (TLs) have been implemented on the 3-µm Top-Metal2
(TM2) layer with Metal3 as the ground plane. The schematic
of the fundamental oscillator is shown in Fig. 2consisting of
an x4 (Ae=4×0.07 µm×0.9 µm) differential CE Colpitts
topology followed by a common-base (CB) stage to provide
isolation. The bases of the CE and CB devices are biased
using current mirror and voltage divider circuits, respectively.
The Colpitts oscillator, including RF pads, is full wave 3-D
electromagentic (EM) simulated with parasitic interconnects
in Ansys HFSS.
A. Oscillator Core
A load–pull simulation was used to analyze the output of the
CE stage, resulting in an impedance of 15 +30 jto enhance
the fundamental voltage and current swings. To achieve this,
the Lcasc inductor was used to transform the input impedance
of the CB stage Zin_CB from 30 +15 jto 15 +30 j
thereby maximizing the voltage and current swings as shown
in Fig. 3. As the oscillation frequency decreases with increas-
ing Lcasc, both Ceand Lbare adapted to maintain a constant
frequency of 220 GHz. Although an Lcasc of 28 pH improves
the current swing by 26% and doubles the voltage swing,
a 10-pH inductor was implemented to ensure a compact
oscillator core size of 70 ×70 µm and provide the required
load impedance of 15 +30 jat the output of the CE device,
and improve the voltage and current swing by 34% and 14%,
respectively.
Fig. 3. Ideal core large signal simulation of the magnitude of 220-GHz
fundamental voltage (left) and current (right) swing at the input of CB device
(across nodes AB) for a varying Lcasc.
Fig. 4. (a) 3-D EM model of the compact 70 ×70 µm oscillator core with the
resonance inductors implemented on TM2. (b) Closed-up highlighting MIM
capacitors implemented on Metal5 (M5) and TM1 buried under inductor Lb.
The 3-D EM model of the 70 ×70 µm compact oscillator
core is shown in Fig. 4consisting of symmetrical differential
inductors Lb,Le, and Lcasc . The emitter inductor Le, extracted
from EM simulations, has a differential inductance of 210 pH
achieving a self-resonance frequency (SRF) of 338 GHz. The
ground under Leis removed to improve the inductance and
quality factor. The differential resonant tank inductor Lbis
implemented directly above the differential CE transistors
having a value of 26 pH, and an SRF of 447 GHz. A 15-
fF resonant tank MIM capacitors Ceare buried under Lbas
shown in Fig. 4. The complete EM simulated oscillator core,
including output matching and the 10-pH Lcasc , shows 30%
improvement in voltage swing and 27% improvement in output
power compared with the core without Lcasc .
B. Output Matching
An optimal differential impedance Zopt of 50 +65 j
after modeling the interconnects up to Top-Metal1 (TM1) at
the oscillator’s output was found through load–pull providing
an ideal output power of 7.8 dBm with a shift in oscillation
frequency to 217 GHz. The outputs have been separated into
two single-ended configurations instead of a balun to reduce
further losses, frequency detuning, and maintain compactness.
The output matching consists of a differential 220-pH shunt
inductor Lcwith 318.7-GHz SRF. A 25-µm-long, 65-sym-
metrical series TLs, and two 70-µm-long, 70-shunt lines
along with the RF pads are implemented on each side along
with large 490-fF dc blocking series capacitors to realize an
impedance of 42 +66 jclose to Zopt .
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CHANDRA PRABHU et al.: 206–220-GHz COMPACT FUNDAMENTAL OSCILLATOR WITH UP TO 7-dBm OUTPUT POWER 3
TABLE I
PER FORM ANCE COMPARISON OF FUND AMEN TA L OSCIL LATORS I N SILICON-BAS ED TECHNOLOGY
Fig. 5. Measurement setup and chip micrograph of the fundamental
differential Colpitts oscillator.
Fig. 6. Measured and simulated differential output power (left) and dc-to-RF
efficiency (right) across the TR of 220.5–206.5 GHz and operated at Vcc/Vcasc
of 3.5/3.2 V.
III. M E AS URE MEN T RES U LTS
Fig. 5shows the measurement setup, including the chip
micrograph. The two single-ended outputs enable simultane-
ous frequency and power measurement with 50-termination
on each side using a J-band WR-03 vector network analyzer
(VNA) extension module connected to an E44404 spectrum
analyzer from Agilent and a VDI-Erickson PM4 power meter
with WR-03 to WR-10 taper. All relevant losses, such as
probe/waveguide losses and conversion gain (CG) of the VNA
extension modules, were calibrated and de-embedded. The
oscillator is operated at a nominal collector (Vcc) and CB base
(Vcasc) bias of 3.5 and 3.2 V, respectively. Fig. 6presents
the measured output power and efficiency across a tuning
range (TR) of 206.5–220.5 GHz, demonstrating excellent
agreement with the simulated results, with an oscillation
frequency variation of <2%. Fig. 7shows the downconverted
output spectrum at 210.7 MHz with a peak of 16.5 dBm
and the corresponding PN of 90.2/110 dBc/Hz and PN
Fig. 7. Measured PN and spectrum of the oscillator operating at 220-GHz
biased at Vcc/Vcasc /Vcm of 3.5/3.2/1.06 V.
figure-of-merit (FoM) of 182/181 dBc/Hz at 1-/10-MHz
offset, respectively. At 220 GHz, the oscillator has an output
power of 5.7 dBm, dc-to-RF efficiency of 7.4%, and dc power
consumption of 50 mW.
IV. CON C LU SIO N
In this work, an efficient 206.5–220.5-GHz fundamental
Colpitts oscillator implemented in a 130-nm SiGe HBT tech-
nology with a peak output power of 7 dBm around 208 GHz
and peak dc-to-RF efficiency of 7.4% at 220 GHz is reported.
The implemented 10-pH inductance at the CB device pro-
vides an inductive load to the CE device and boosts the
output power by 27%. This design has the best PN FoM of
182/181 dBc/Hz at 1-/10-MHz offset as compared to the
SOTA for silicon-based oscillators above 200 GHz presented
in Table I. Therefore, based on its ultracompact 0.0049 mm2
core size, the presented oscillator is suitable for large-scale
source arrays for high-resolution THz light-field imaging.
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This article proposes a fundamental frequency oscillator topology that efficiently extracts maximum power from the transistors while minimizing the effective parasitic capacitance, leading to a further increase in output power by enabling the adoption of larger size transistors. High-power fundamental oscillators operating at 150 and 245 GHz are designed using the proposed topology. Implemented in a 40-nm CMOS technology, the proposed 150-and 245-GHz oscillators achieve a peak output power of 12.1 and - 2.54 dBm, a peak dc-to-RF efficiency of 14.3% and 1.2%, and a phase noise at 1 MHz of - 98.2 and - 86.3 dBc/Hz, respectively. The corresponding figure-of-merit (FoM/FoM A_{A} ) values of the proposed 150-and 245-GHz oscillators are - 193/ - 202 and - 175/ - 186 dBc/Hz, respectively.
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This article presents a 205–273-GHz wideband frequency multiplier chain (FMC) in a 0.13- μ\mu m SiGe BiCMOS technology with fT/fmaxf_{\mathrm{T}}\text{/}f_{\mathrm{max}} = 300/500 GHz. The proposed FMC consists of a Q -band input transformer (TF) balun, an F -band frequency tripler, an F -band power amplifier (PA), and a G -/ J -band frequency doubler, which results in a sixth multiplier. To obtain high output power and high efficiency, a two-way power combining push–push doubler with second harmonic resonators is introduced. The high quality factor ( Q -factor) cross-fingers capacitor is employed in the wideband output matching network to reduce the insertion loss (IL). A wideband PA is utilized to drive the following doubler. The frequency tripler with an adaptive bias circuit is proposed to exhibit high output power while relatively flat conversion gain (CG), with which the output power of the tripler can be easily controlled. An analysis of the input TF balun is introduced for improving the common mode rejection, which results in high even harmonic suppression of the tripler. The proposed FMC exhibits 9-dBm saturated output power ( Psat)P_{\mathrm{sat}}) , with a 3-dB bandwidth of 68 GHz. The dc-to-RF efficiency of 1.92% is achieved with more than 10-dB CG at 252 GHz. The FMC consumes less than 0.5 W and occupies a small chip area. To the best of our knowledge, the proposed FMC exhibits the highest PsatP_{\mathrm{sat}} and dc-to-RF efficiency in silicon-based implementations beyond 200 GHz.
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We present an optimization-based design methodology for high-power and high-efficiency millimeter-wave fundamental oscillators in CMOS. The optimization is formulated to take into account the loss of the passive components to result in an optimal circuit design. Compared with previous methods, the proposed approach can produce the final design in a single pass of optimization with a fast and robust convergence profile. In this article, we also present a comparative study between the T- and the Π\Pi -embedding networks and show that T-embedding is superior to Π\Pi -embedding in terms of flexibility in biasing and sensitivity to component Q . As such, we argue that our design approach can target high output power and high efficiency separately to result in an optimal design for a given application. A design example of a 215-GHz fundamental oscillator in a 65-nm CMOS technology is presented to demonstrate the effectiveness of the proposed design approach. The oscillator achieves 5.17-dBm peak output power at 1.2-V supply with a corresponding dc-to-RF efficiency 12.3% and a peak efficiency of 13.7%. The measured phase noises are 90.0-90.0 and 116.2-116.2 dBc/Hz at 1 and 10 MHz offset, respectively. A second design example at 310 GHz also demonstrates state-of-the-art performance with a peak output power of 4-4 dBm and dc-to-RF efficiency of 3.2%.
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This letter proposes a 300 GHz high output power and high efficiency push-push coupling voltage-controlled oscillator using T-embedded network. To achieve high output power, eight single-ended T-embedding oscillators are coupled together. The second harmonic of oscillators is extracted by push-push topology and the output power is combined. The procedure of realizing optimal second harmonic output power is introduced and the approach to synthesizing components’ parameter of embedded network is presented. Measurement result shows that the proposed coupling oscillator can be tuned from 297 to 305 GHz and delivers 2.8 dBm output power with peak efficiency of 2.85%. The measured phase noise at 10 MHz offset frequency is about −96 dBc/Hz for center frequency.
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Based on the polyharmonic distortion (PHD) method, we present an approach to find the optimum conditions for efficient second-harmonic signal generation in millimeter-wave (mm-wave) harmonic oscillators that also maximize their DC-to-RF efficiency. These conditions include magnitude and phase of voltages at the gate and drain of the core transistors at both fundamental and second-harmonic signal components as well as the DC bias point to generate the maximum achievable second-harmonic power. We also establish that the steady-state oscillation at the fundamental frequency is a crucial criterion to obtain such conditions. The maximum achievable power and efficiency obtained from the proposed approach are independent of the harmonic oscillator topology and hence can be regarded as a reference for comparing different design techniques and structures. According to the proposed design procedure, the optimum conditions for an nMOS transistor acting as the active core of a 200-GHz harmonic oscillator are found and a second-order harmonic oscillator topology that can fulfill the optimum conditions is proposed. The oscillator is designed and fabricated in a 65-nm CMOS process and achieves peak DC-to-RF efficiency of 6.05%. The peak output power at 1.2-V supply is 2.9 dBm at 203 GHz.
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This letter presents a 220–261-GHz frequency multiplier-by-18 chain in a 130-nm SiGe BiCMOS technology. It consists of three amplifiers (12–15, 110–135, and 216–270 GHz), two frequency triplers (36–45 and 108–135 GHz), a third-order Chebyshev bandpass filter (36–45 GHz), and a modified Gilbert-cell-based frequency doubler (216–270 GHz). The peak output power is about 8 dBm at 240 GHz with a 3-dB bandwidth of 41 GHz for an input power of −7 dBm. The unwanted harmonics are suppressed more than 25 dBc over the frequency range of interest. It consumes a dc current of 114.7 mA from a supply voltage of 3.3 V in the quiescent operation and drains a current of 130 mA for an input power of −7 dBm, which results in a drain efficiency of 1.47%. The total circuit occupies an area of 0.58 mm 2 (1.35 mm ×0.43\times0.43 mm).