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Overcoming Welding and Contact Degradation Failures Incurred by Complementary N/MEMS Logic Gate Structures Fabricated on SOI Wafers
Abstract
Nano/microelectromechanical systems (N/MEMS) based complementary logic circuits offer a physically robust alternative to conventional CMOS control systems, which are able to function in environments unsuitable for transistor devices. In this work we demonstrate novel, configurable, complementary logic circuits comprised entirely of relays at both NEMS and MEMS scale, which are capable of fulfilling all primary logic functions. Lifetime testing of the fabricated devices revealed two key failure modes: contact degradation and welding of high voltage cantilevers, both of which are caused by the charging and discharging of unwanted parasitic capacitances inherent to complementary relay structures. Devices are consequently damaged by high transient current and arc discharge between contacts. Several solutions are proposed and implemented to mitigate these issues, including minimization of unwanted capacitances, optimization of metallization scheme, introduction of intermediate operation cycles intended to increase time between state changes, and prevention of welding by preemptively charging capacitors to an intermediate voltage. To this effect, a detailed study of lifetimes for both single cantilevers and logic gate structures is presented comparing a variety of metallization schemes using Pt, Ti, TiN, and W, including their multilayer combinations. These varied optimization methods yielded single cantilever lifetimes of 1.74 billion cycles on average for devices with a Ti adhesion layer, a Pt primary layer, and a W surface layer to increase durability. Using the same metallization scheme, complementary logic structures achieved 0.6 million cycles on average. These results demonstrate the viability of robust N/MEMS based complementary logic circuits for safety critical control applications. 2024-0203
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Cryogenic deep reactive ion etching (Cryo DRIE) of silicon has become an enticing but challenging process utilized in front-end fabrication for the semiconductor industry. This method, compared to the Bosch process, yields vertical etch profiles with smoother sidewalls not subjected to scalloping, which are desired for many microelectromechanical systems (MEMS) applications. Smoother sidewalls enhance electrical contact by ensuring more conformal and uniform sidewall coverage, thereby increasing the effective contact area without altering contact dimensions. The versatility of the Cryo DRIE process allows for customization of the etch profiles by adjusting key process parameters such as table temperature, O2 percentage of the total gas flow rate (O2 + SF6), RF bias power and process pressure. In this work, we undertake a comprehensive study of the effects of Cryo DRIE process parameters on the trench profiles in the structures used to define cantilevers in MEMS devices. Experiments were performed with an Oxford PlasmaPro 100 Estrelas ICP-RIE system using positive photoresist SPR-955 as a mask material. Our findings demonstrate significant influences on the sidewall angle, etch rate and trench shape due to these parameter modifications. Varying the table temperature between −80 °C and −120 °C under a constant process pressure of 10 mTorr changes the etch rate from 3 to 4 μm min⁻¹, while sidewall angle changes by ∼2°, from positive (<90° relative to the Si surface) to negative (>90° relative to the Si surface) tapering. Altering the O2 flow rate with constant SF6 flow results in a notable 10° shift in sidewall tapering. Furthermore, SPR-955 photoresist masks provide selectivity of 46:1 with respect to Si and facilitates the fabrication of MEMS devices with precise dimension control ranging from 1 to 100 μm for etching depths up to 42 μm using Cryo DRIE. Understanding the influence of each parameter is crucial for optimizing MEMS device fabrication.
A thorough understanding of arc discharge mechanism as well as determination of arc discharge voltage at the nanometer scale remains challenging due to the complexities associated with electrode preparation and precisely maintaining nanoscale separations in experiments. This work addresses this challenge through a novel approach by accurately measuring electric breakdown/discharge voltages between Pt-coated Si electrodes with separations ranging from ∼5 nm to 370 nm using a combination of fixed and flexible nano-electrodes while inherently creating an ideal environment to mitigate the effect of mechanical vibrations on the measurement results. For separations of 10, 100, and 300 nm, the corresponding discharge voltages are ∼15, 75, and 160 V, respectively, with the apparent electric field for the 10 nm separation exceeding 1.5 GV m⁻¹. The results acquired from the investigated electrode configuration closely resembling the laterally actuated nanoelectromechanical system (NEMS) cantilever relays reveals strong agreement with NEMS relay breakdown characteristics, emphasizing the importance of arc discharge considerations while designing micro/nano electromechanical devices. Furthermore, deliberately applied arc discharge is shown to provide electrode nano-welding for realization of configurable NEMS circuits.
We measure the stiction force using in-plane electrostatically actuated Si nanoelectromechanical cantilever relays with Pt contacts. The average current-dependent values of the stiction force, ranging from 60 nN to 265 nN, were extracted using the I DS vs V GS hysteresis curves, the cantilever displacement information from finite element method (Comsol Multiphysics) simulations, and the force distribution determined using an analytical model. It is shown that the stiction force is inversely and directly proportional to the contact resistance (R c) and drain-source current (I DS), respectively. Using the dependence of the stiction force on the contact current, we demonstrate the tuning of the voltage hysteresis for the same relay from 8 V to 36 V (equivalent to a stiction force of 70 nN to 260 nN, respectively). We attribute the stiction force primarily to the metallic bonding force, which shows a strong dependence on the contact current.
With the exponential growth of the semiconductor industry, radiation-hardness has become an indispensable property of memory devices. However, implementation of radiation-hardened semiconductor memory devices inevitably requires various radiation-hardening technologies from the layout level to the system level, and such technologies incur a significant energy overhead. Thus, there is a growing demand for emerging memory devices that are energy-efficient and intrinsically radiation-hard. Here, we report a nanoelectromechanical non-volatile memory (NEM-NVM) with an ultra-low energy consumption and radiation-hardness. To achieve an ultra-low operating energy of less than 10 fJ bit−1, we introduce an out-of-plane electrode configuration and electrothermal erase operation. These approaches enable the NEM-NVM to be programmed with an ultra-low energy of 2.83 fJ bit−1. Furthermore, due to its mechanically operating mechanisms and radiation-robust structural material, the NEM-NVM retains its superb characteristics without radiation-induced degradation such as increased leakage current, threshold voltage shift, and unintended bit-flip even after 1 Mrad irradiation. Achieving both low energy consumption and radiation-hardness is highly challenging in memory devices. Here, the authors demonstrate a sub-10 fJ/bit, radiation-hard nanoelectromechanical non-volatile memory through structural and material approaches.
The current electromechanical and solid-state relays employed in the Nuclear PowerInstrumentation and Control (I&C) are outdated and subjected to maintenance and reliabilitychallenges primarily related to degradation caused by ageing, high voltage/current operations,electromagnetic interference ( EMI), and non -ionizing and ionizing radiation. To address theseconcerns, we assert that significant performance and cost advantages may be gained by shifting tomicro- and nano-scale electromechanical relays for I&C applications in nuclear power plants(NPPs). Single-crystal silicon is well known to be extremely resistive to material fatigue and creepdeformation, providing superior reliability of electromechanical actuation. Each micro-scaled relaycan be situated within a 2 mm x 2 mm area and nano-scaled relays may be implemented to have a 200 μm x 200 μm footprint. A single Si wafer (e.g., 100 mm in diameter) can then incorporate alarge number of relays produced in a single fabrication run and each relay, based on a cantilever that moves laterally under electrostatic attraction, can be uniquely designed and fabricated to operate ata specific turn-on (actuation) voltage. Moreover, these relays on the same wafer can be interconnected as desired to perform a variety of logic operations. In this work, we present the novelfabrication methods and test results for both micro- and nano-scale relays. Although micro- and nano-scale devices involve lithographic processes of different scales, the resultant operation of the fabricated relays is tested in the same manner. As an initial viability test, micro- and nano-scaled cantilever modeling simulations with actuation voltages (Vpi) of 10 – 45V are compared against analytical models showing a 3 - 4 % difference between them. Furthermore, simulated testing to ascertain the stress response of cantilevers suggest a potential fatigue lifetime of > 10 billion cycles. Additionally, preliminary DC and AC ON/OFF switching characteristics of fabricated nano-scalerelays were found to have actuation voltages (Vpi) near ~43V.
In this study, a new analytical model is developed for an electrostatic Microelectromechanical System (MEMS) cantilever actuator to establish a relation between the displacement of its tip and the applied voltage. The proposed model defines the micro-cantilever as a rigid beam supported by a hinge at the fixed-end with a spring point force balancing the structure. The approach of the model is based on calculation of the electrostatic pressure centroid on the cantilever beam to localize the equivalent electrostatic point load. Principle outcome of the model is just one formula valid for all displacements ranging from the initial to the pull-in limit position. Our model also shows that the pull-in limit position of a cantilever is approximately 44% of the initial gap. This result agrees well with both simulation results and experimental measurements reported previously. The formula has been validated by comparing the results with former empirical studies. For displacements close to the pull-in limit, the percentage errors of the formula are within 1% when compared with real measurements carried out by previous studies. The formula also gives close results (less than 4%) when compared to simulation outcomes obtained by finite element analysis. In addition, the proposed formula measures up to numerical solutions obtained from several distributed models which demand recursive solutions in structural and electrostatic domains.
The need for more energy-efficient solid-state switches beyond complementary metal-oxide-semiconductor (CMOS) transistors has become a major concern as the power consumption of electronic integrated circuits (ICs) steadily increases with technology scaling. Nano-Electro-Mechanical (NEM) relays control current flow by nanometer-scale motion to make or break physical contact between electrodes, and offer advantages over transistors for low-power digital logic applications: virtually zero leakage current for negligible static power consumption; the ability to operate with very small voltage signals for low dynamic power consumption; and robustness against harsh environments such as extreme temperatures. Therefore, NEM logic switches (relays) have been investigated by several research groups during the past decade. Circuit simulations calibrated to experimental data indicate that scaled relay technology can overcome the energy-efficiency limit of CMOS technology. This paper reviews recent progress toward this goal, providing an overview of the different relay designs and experimental results achieved by various research groups, as well as of relay-based IC design principles. Remaining challenges for realizing the promise of nano-mechanical computing, and ongoing efforts to address these, are discussed.
The adherence of Platinum thin film on Si/SiO2 wafer was studies using Chromium, Titanium or Alumina (Cr, Ti, Al2O3) as interlayer. The adhesion of Pt is a fundamental property in different areas, for example in MEMS devices, which operate at high temperature conditions, as well as in biomedical applications, where the problem of adhesion of a Pt film to the substrate is known as a major challenge in several industrial applications health and in biomedical devices, such as for example in the stents.1-4 We investigated the properties of Chromium, Titanium, and Alumina (Cr, Ti, and Al2O3) used as adhesion layers of Platinum (Pt) electrode. Thin films of Chromium, Titanium and Alumina were deposited on Silicon/Silicon dioxide (Si/SiO2) wafer by electron beam. We introduced Al2O3 as a new adhesion layer to test the behavior of the Pt film at higher temperature using a ceramic adhesion thin film. Electric behaviors were measured for different annealing temperatures to know the performance for Cr/Pt, Ti/Pt, and Al2O3/Pt metallic film in the gas sensor application. All these metal layers showed a good adhesion onto Si/SiO2 and also good Au wire bondability at room temperature, but for higher temperature than 400 °C the thin Cr/Pt and Ti/Pt films showed poor adhesion due to the atomic inter-diffusion between Platinum and the metal adhesion layers.5 The proposed Al2O3/Pt ceramic-metal layers confirmed a better adherence for the higher temperatures tested.
This work presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay circuits designed on these test chips illustrate a range of important functions necessary for the implementation of integrated VLSI systems and lend insight into circuit design techniques optimized for the physical properties of these devices. To explore these techniques a hybrid electro-mechanical model of the relays' electrical and mechanical characteristics has been developed, correlated to measurements, and then also applied to predict MEM relay performance if the technology were scaled to a 90 nm technology node. A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area.
To overcome the energy-efficiency limitations imposed by finite sub-threshold slope in CMOS transistors, this paper explores the design of integrated circuits based on nanoelectro-mechanical (NEM) relays. A dynamical Verilog-A model of the NEM relay is described and correlated to device measurements. Using this model we explore NEM relay design strategies for digital logic and I/O that can significantly improve the energy efficiency of the whole VLSI system. By exploiting the low effective threshold voltage and zero leakage achievable with these relays, we show that NEM relay-based adders can achieve an order of magnitude or more improvement in energy efficiency over CMOS adders with ns-range delays and with no area penalty. By applying parallelism, this improvement in energy-efficiency can be achieved at higher throughputs as well, at the cost of increased area. Similar improvements in high-speed I/O energy are also predicted by making use of the relays to implement highly energy-efficient digital-to-analog and analog-to-digital converters.
Nano electro-mechanical systems (NEMS) based combinational logic circuits have garnered attention as possible replacements for electronic logic systems in safety critical environments where conditions make the use of electronics non-ideal. The principal advantages of NEMS are the inherent near zero leakage current and ability to operate in harsh conditions where substantial parasitic field effects are present. In this work, we design and experimentally demonstrate NEMS based logic gates which utilize multi-gate relays, designed to actuate when input signals are applied to all gate terminals simultaneously. This design enables signal propagation through a single relay for NAND, NOR, and NOT gates with any number of inputs, eliminating variations of output resistance and capacitance, which affect the output generation time. Furthermore, these devices are fabricated using a conventional process requiring only one lithography step. These devices can be utilized to produce all primary logic functions. The proposed platform exclusively uses relay structures based on straight cantilevers, favoring a complementary logic, and allowing for the aforementioned improvements over current designs. The relay structures are optimized using a procedure based on COMSOL simulations. The efficacy of the logic gate designs, and corresponding optimization procedures are validated through a series of electrical tests on fabricated 3-input NAND gate structures utilizing a multi-gate relay. The tests show successful operation for input voltages ranging from 62 and 74 V thus confirming that the approach put forth in this paper can effectively constitute NEMS based complementary logic circuits, while fulfilling all constituent input and output requirements. 2023-0125
Nano/micro-electromechanical (NEM/MEM) contact switches have great potential as energy-efficient and high-temperature-operable computing units to surmount those limitations of transistors. However, despite recent advances, the high-temperature operation of the mechanical switch is not fully stable nor repetitive due to the melting and softening of the contact material in the mechanical switch. Herein, MEM switches with carbon nanotube (CNT) arrays capable of operating at high temperatures are presented. In addition to the excellent thermal stability of CNT arrays, the absence of a melting point of CNTs allows the proposed switches to operate successfully at up to 550 °C, surpassing the maximum operating temperatures of state-of-the-art mechanical switches. The switches with CNTs also show a highly reliable contact lifetime of over 1 million cycles, even at a high temperature of 550 °C. Moreover, symmetrical pairs of normally open and normally closed MEM switches, whose interfaces are initially in contact and separated, respectively, are introduced. Consequently, the complementary inverters and logic gates operating at high temperatures can be easily configured such as NOT, NOR, and NAND gates. These switches and logic gates reveal the possibility for developing low-power, high-performance integrated circuits for high-temperature operations.
This manuscript focuses on Nano-Electro-Mechanical (NEM) relays with electrostatic actuation for advanced logic and memory applications. The use of Nano-Electro-Mechanical relays was recently proposed for digital logic circuits in order to overcome the fundamental energy-efficiency limitations that mainstream CMOS technology is currently facing. The cumulated benefits of essentially Zero Off-State current and ultimately abrupt DC switching characteristics enable alleviating the power-performance trade-off as the supply voltage VDD is reduced. Additionally, for some particular switch designs (e.g. free of dielectric layers), an increased resistance to ionizing radiations is also anticipated, making such components valuable for defense or aerospace applications.However, NEM relays have intrinsic limitations in terms of integration density, endurance and operation frequency. Therefore, rather than considering them as technology that could replace MOSFETs, we adopt an intermediate approach that consists in using NEM relays as a complement to CMOS circuits (e.g.: buffers, non-volatile elements for SRAM and CAM), which can be fabricated in a 3D co-integration scheme. This approach mitigates the area penalty issue.The thesis explores the strength and the weakness of NEMS relays and identifies applications for which hybrid NEMS/CMOS circuits are potentially interesting.This work includes the manufacturing of prototype devices designed to be proof of concept for the identified applications. At first, NV NEM relays design and dimensioning through modelling and simulations was performed. Then NV NEM/CMOS circuits were validated trough simulations. This was followed by the tapeout and the process integration of monolithically co-integrated NEMS above CMOS. After wafer processing the devices were electrically characterized.This all-inclusive works allows identifying some crucial challenges that NEMS relays still have to face.
As transistors are reaching their fundamental limits in terms of power consumption, miniaturization, and heat generation, there is an imminent need to develop alternate computing technologies. One such an alternative is through micro/nanoelectromechanical systems (M/NEMS) that focuses on ultra-low energy consumption. Computing based on static MEMS switches has been proposed, however these suffer from reliability issues due to contact and stiction. Recently, logic devices based on electro mechanically excited vibrating structures, resonators, have emerged as a potential solution that overcomes these issues. This paper reviews the recent advancements of resonator-based M/NEMS logic devices. First, pioneering works in the field are surveyed. Then, logic devices based on frequency tuning are discussed. Next, cascadability of such logic devices is demonstrated. Finally, a discussion about the challenges of such technology and future prospects is presented.
Microelectromechanical systems (MEMS) or nanoelectromechanical systems (NEMS) switches are of interest for applications ranging from radio frequency (RF) communication circuitry to power surge protection to low power computing. Reliable operation of the switch contacts is critical. Many researchers have investigated the effect of different materials on reliability, but little work has been reported on the effects of process conditions. In this study, the effects of the angle of deposition incidence, the microstructure, the interface adhesion, the base pressure, and the process transferability have been evaluated in Pt-coated MEMS switches. Among them, base pressure attained prior to deposition was most important, while an interaction between electrode geometry and film microstructure was also identified to play a role. A lower base pressure (2•10⁻⁶ Torr) improved cycle count significantly while a higher base pressure (8•10⁻⁶ Torr) resulted in low cycle counts (10⁶ or less). Failure analysis indicated surface wear due to damage at a corner junction, where films deposited at different angles of deposition incidence meet. Mass spectroscopy analysis detected higher carbon content in Pt films with high base pressure. This suggests that grain boundaries weakened by impurity segregation exacerbated the geometric effect. Switches tested in a follow-up experiment, in which the base pressure was 5•10⁻⁷ Torr, again resulted in high cycle counts (330•10⁶), reinforcing the importance of achieving low base pressure in improving the mechanical reliability of the corner junction.
This paper presents the design, fabrication, and evaluation of electrostatically driven nanoelectromechanical (NEM) switches and logical gates, including NAND and NOR gates. The conformal deposition of tungsten (W) on high aspect ratio structures is investigated by selective W chemical vapor deposition (CVD) as an electrical contact material. The switching characteristics of the NEM switches, as well as their pull‐in voltages, are evaluated. Logical gates, including NAND and NOR gates, are formed by the four NEM switches consisting of four cantilevers, two input ports, two source ports, and an output. Devices are successfully fabricated by a combination of an electron beam lithography, a deep reactive ion etching, and a selective W CVD. The truth table operations for the NAND and NOR gates are examined and demonstrated in this paper.
Titanium nitride (TiN) is of interest as a material in MEMS and NEMS switches due to its high hardness, low-surface energy, good electrical conductivity, and resistance to chemical oxidation. We perform extensive characterization of TiN for microswitches. We optimize process parameters to attain low resistivity (
) and acceptable residual stress. A specific resistivity of
cm
2
is achieved, about 50 times lower than previous reports. We successfully wedge bond to the TiN with Al wire using high ultrasonic power. Because surface stoichiometry of binary alloys may depend on mechanochemical effects, we cycle test in controlled O
2
, N
2
, Ar, and N
2
:C
6
H
6
gas environments. Of these, O
2
yielded short lifetimes (~100 cycles), while N
2
and Ar gave equivalent results (~10
5
cycles). The N
2
:C
6
H
6
environment enabled the longest lifetimes (
cycles) at the expense of increasing
ECR
. The cycle count limit in N
2
and Ar was investigated and traced to a weak microstructure that develops at corners of the contacting surfaces. If such corners are avoided in future designs, TiN-coated switches likely can survive to much higher cycle counts. [2018-0158]
This work reports a TiN coated contact implemented in a vertically actuated SiGe-based Nano-Electro-Mechanical (NEM) relay. It is shown that covering the bottom of the movable SiGe beam (the armature) with a TiN layer in the contact region will improve the contact performance of the relay with lowering the on-resistance, R ON , by around 4 orders of magnitude and by enhancing the number of switching cycles without degradation. This NEM relay provides an optimal combination of small motional volume (∼0.02µm 3 ) and long mechanical lifetime (> 10 10 in vacuum). Furthermore, with a total contact area of 0.01µm 2 (among the smallest reported so far), an on-resistance of ∼1MΩ has been achieved.
Since mechanical switches (relays) have zero off-state leakage and perfectly abrupt ON/OFF switching behavior, in principle they can be operated with a very small voltage swing and overcome the energy efficiency limit of CMOS technology. This paper discusses recent developments to address the remaining technical challenges for fully realizing the promise of ultra-low-power mechanical computing.
In this paper, a detailed analysis and comparison of nanoelectromechanical systems (NEMS) and CMOS technologies for low power adiabatic logic implementation is presented. Fundamental limits of CMOS-based adiabatic logic are identified. Analytic relations describing the energy-performance for sub-threshold adiabatic logic are also explicitly derived and optimized. The interest of combining NEMS technology and adiabatic logic is described, and the key NEMS switch parameters that govern the dissipation-performance relationship are identified as the switch commutation frequency, its actuation voltage, and the contact resistance between the switch electrodes. Furthermore, NEMS-based adiabatic gates architectures are described. Finally, the contribution of the power-clock or energy recovery generator is estimated in order to compare CMOS and NEMS-based adiabatic architectures at the system level. The paper concludes with a detailed comparison of the energy-performance of the different explored technologies.
This paper reports the design optimization of lateral nanoelectromechanical (NEM) relays for sub 1V actuation by COMSOL simulation with various materials and structures. Measured actuation voltages from fabricated relays showed good matching with simulation.
Laterally actuated polycrystalline silicon nanoelectromechanical (NEM) relays with enhanced electrical properties are presented. Due to surface oxidation of polysilicon in room ambient conditions, the relays have a high contact resistance (> 1 GΩ) that requires high drain bias (3-5 V) to break through. The addition of a platinum sidewall coating reduces the on-resistance and the required drain bias to as low as 3 kΩ and 0.1 V, respectively. The platinum coating's stability is demonstrated by two tests: first, a contact-and-hold test where the relay passes current (~1μA) for up to 155 min and, second, a hot cycling test where the relay survives for over 10
8
cycles . The NEMS relays are simulated using finite-element analysis, and the models are verified against experimental tests. Furthermore, the relays are configured and tested as a 2 : 1 multiplexer to show their potential as a digital logic component.
The impact of device operating parameters on the on-state resistance of microelectromechanical relays with tungsten (W) electrodes is reported. Due to the susceptibility of W to oxidation, increases undesirably over the device operating cycles. This issue is aggravated by Joule heating when the relay is in the on state. The experimental results confirm that shorter on time, as well as shorter off time, provides for more stable with respect to the number of on/off switching cycles.\hfill[2011-0370]
In this paper, we introduced for the first time the energy-reversible complementary nanoelectromechanical (ER CNEM) logic gates and demonstrated their superiority over the conventional relays in terms of voltage, energy, and reliability. The ER CNEM logic a promising candidate for low standby and low operating power applications.
Nanoelectromechanical (NEM) switches are similar to conventional semiconductor switches in that they can be used as relays, transistors, logic devices and sensors. However, the operating principles of NEM switches and semiconductor switches are fundamentally different. These differences give NEM switches an advantage over semiconductor switches in some applications--for example, NEM switches perform much better in extreme environments--but semiconductor switches benefit from a much superior manufacturing infrastructure. Here we review the potential of NEM-switch technologies to complement or selectively replace conventional complementary metal-oxide semiconductor technology, and identify the challenges involved in the large-scale manufacture of a representative set of NEM-based devices.
This paper reports on the modeling, fabrication, and testing of cantilever- and parallel plate-based laterally actuated platinum-coated polysilicon nanoelectromechanical (NEM) relays. The polysilicon acts as the structural layer, while the platinum serves as a conducting contact material, as well as a local routing layer. The two-part cantilever design utilizes a source made of a compliant beam in series with a stiff bridged perimeter electrode to reduce the secondary pull-in of the source to the gate. The parallel-plate-based relay also uses stiffened electrodes in addition to serpentine structures that reduce the actuation voltage. Overdrive gate voltage in excess of 100% without failure and sharp release of the relay from output are achieved for polysilicon relays with 50nm platinum coating and 500nm actuation gap.
Logic circuits capable of operating at high temperatures can alleviate expensive heat-sinking and thermal-management requirements
of modern electronics and are enabling for advanced propulsion systems. Replacing existing complementary metal-oxide semiconductor
field-effect transistors with silicon carbide (SiC) nanoelectromechanical system (NEMS) switches is a promising approach for
low-power, high-performance logic operation at temperatures higher than 300°C, beyond the capability of conventional silicon
technology. These switches are capable of achieving virtually zero off-state current, microwave operating frequencies, radiation
hardness, and nanoscale dimensions. Here, we report a microfabricated electromechanical inverter with SiC complementary NEMS
switches capable of operating at 500°C with ultralow leakage current.
The operation and performance of complementary nanoelectromechanical (CNEM) logic gates are investigated. NEMS structures featuring dimensions 2 to 3 orders of magnitude smaller than the present MEMS relays are considered. Various metals are benchmarked to silicon as the cantilever beam material. We show that the CNEM inverters featuring laterally actuated beams, 10 nm gap and low density materials such as Si or Al can achieve nanosecond pull-in delay and sub-0.1 fJ switching energy at VDD = 1.5 V while occupying an area as small as 0.03 mum2.
IEEE NANO 2017: 17th International Conference on Nanotechnology
Nano-patterned Si structures for optical filters and electro-mechanical relays: Fabrication, characterization, prospects, and limitations
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