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On-chip assessment procedure and calibration structure for aging
durability assessment of integrated circuits
Mehul Manu
School of Allied Sciences, Graphic Era Hill University Bhimtal Campus, Nainital, India
Saurabh Dhanik
School of Computing, Graphic Era Hill University, Bhimtal Campus Nainital, India
Kashish Mirza & Rashmi Deopa
Computer Science and Engineering, Graphic Era Hill University, Bhimtal Campus Nainital,
India
Shewta Goyal
Department of Electrical Engineering, Graphic Era Deemed to be University,
Dehradun India
ABSTRACT: In this article, we have proposed a quantitative evaluation approach and an
on-chip calibration architecture to evaluate the aging reliability of Integrated circuits (ICs).
The on-chip calibration architecture comprises a configurable ring oscillator, an edge
detection circuit, and a test and control module. The return path of the configurable ring
oscillator is used for calibration to achieve precise clock cycle. The matching path is inte-
grated with the ring oscillator to configure the time delay of the buffer path to match the key
path. The edge detection circuit enables the calibration of the matching path. The test and
control module are used to control the processing mode of the calibration architecture. The
calibration architecture can achieve in-situ calibration of the time delay of the key path
under different power supply voltages, which can be used to predict the burn-in speed of the
critical path. The aging reliability evaluation process involves a fast aging reliability assess-
ment method for the IC. We also designed an on-chip calibration architecture for real-time
time delay calibration of the key path during normal circuit operation to keep track of the
aging process.
Keywords: Integrated circuit, aging durability, assessment procedure, on-chip calibration
structure, configurable ring oscillator, edge detection circuit, test and control module, time
delay calibration, critical path, burn-in speed, power supply voltage
1 INTRODUCTION
Modern electronic structures rely on Integrated circuits to power applications ranging
from consumer electronics to automotive and aerospace structures. The need for more
performance, more functionality, and less integrated circuit (IC) size remains key as ICs
remain crucial. With this need, the need for aging durability of the ICs rises. IC’s age when
exposed to electrical stress, which is as a result of the thermal cycle and material depletion
among other factors. Thus, the assessment of the IC’s aging durability is of key significant
in microelectronics [1–5]. The ICs aging durability involves the degradation of the IC’skey
848 DOI: 10.1201/9781003559085-145
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Challenges in Information, Communication and Computing Technology –V. Sharmila et al. (Eds)
© 2025 The Author(s), London, 978-1-032-90166-4
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components and of which basis the assessment is done. Aging mainly affects the critical
path, and thus the key measurement to time delay of the process. The measurement of the
process is done based on the time delays of the longest delay path of the circuit where real-
time measurement gives the aging progression and IC failure mechanism. Traditional
assessment methods involve accelerated aging test, temperature cycle, and stress tests,
which leads to; prolonged test time, external calibrations stage, and numerous resources.
There is, therefore, a need for a simplified method that ensures the measure of the time
delay of critical paths, careering prediction speed, and the assessment of the aging process.
The assessment we sought to present is on the novel assessment procedure and the on-chip
calibration structure for the assessment of ICs. The procedure involves structure of the
configurable ringed oscillator, edge detection circuit, and the assessment and control
module. The ring oscillator plays the key part in the measurement of time delay along the
critical direction. The structure is designed based on flexibility to adjust the delay char-
acteristics of the path for accurate calibrating and matching of the buffers and key paths of
the IC [6–10].
To conclude, this article introduces a new assessment process and calibration structure
on-chip for evaluating the aging durability of ICs. An edge detection circuit, a test and
control module, and a configurable ring oscillator make up the structure; the method
allows precise time delay calibrations along the critical path . The procedure allows quick
aging durability evaluation and prediction of the burn-in speed, as well as real-time
monitoring of the IC’s aging degree. These stunningly complex advancements in aging
durability assessment pave the way for the manufacturing of high-quality, reliable ICs for
more resilient and sturdy electronic structures throughout today’s life. .8 It ensures the
precise identification of signal edges and the alignment of the time delays of both the buffer
and key paths [11–13]. The calibration can fully account for variations or disparities
between the two paths through precise edge detection, increasing the aging durability and
accuracy of calibrations.
2 RELATED WORK
An integrated circuit (IC) is a microelectronic device that integrates various components and
their interconnecting wires onto a small silicon chip using semiconductor manufacturing
processes. It offers significant advantages such as miniaturization, low power consumption,
high durability, and cost-effectiveness [14–19]. ICs can be classified into analog, digital, and
hybrid types based on their functions and structures. With the advancement of silicon
technology, the gate length of advanced Complementary Metal Oxide Semiconductor
(CMOS) devices continues to decrease. However, this reduction in gate length, without a
corresponding decrease in supply voltage, leads to increased current density and exacerbates
aging effects within the transistors. The aging effects in ICs primarily include static bias
instability effects (NBTI), hot carrier injection effects (HCI), time-dependent dielectric
breakdown effects (TDDB), and electron mobility effects (EM). Among these, NBTI and
HCI are considered the main aging effects that determine the lifetime of an IC. Moreover,
the aging effects become more pronounced in deep sub-micron ICs due to increased manu-
facturing uncertainties, resulting in varying burn-in speeds among different ICs.
Consequently, even if IC chips pass structural and functional tests, they can still face failure
problems during practical use due to aging effects [19–25].To address these issues, this
research presents utilizing the initial threshold voltage of the critical path as a key parameter
for assessment the aging durability of ICs and employs an on-chip test structure to rapidly
test the initial threshold voltages of different critical paths [26–30]. The on-chip test structure
offers high calibration precision and enables individual prediction of the aging durability of
ICs while simultaneously detecting the actual aging condition of the circuit during use. A
procedure to predict NBTI aging based on IDDQ testing published by K. Kang et al. in
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2007 measured the leakage current of an IC in the standby state. This procedure, however,
exhibited poor correlation to actual aging speed of critical paths and required an external
testing device. Another aging prediction procedure based on measuring the threshold voltage
was published by Velamina et al. in 2012, but the procedure required additional test equip-
ment and lacked this testing modality as a part of IC design. A critical path fast-aging
prediction procedure was based on the measurement of the initial threshold voltage of ring
oscillator, and it was published by Wang et al. in 2014. By applying the initial threshold
voltage of critical paths and utilizing the integrated on-chip test using multi-stage LFSR, this
approach achieves precise aging speed prediction and provides real-time monitoring of ICs’
aging condition. It hopes to provide a solution to the issue of implementation of robustness
assessment of individual ICs, thereby fostering the advancement of more durable and reli-
able ICs. ICs and contribute to the development of more robust and reliable integrated
circuits.
3 METHODOLOGY
This research presents an on-chip calibration structure for evaluating the aging of an
integrated circuit based on the following three components: The control test comprises a
configurable ring oscillator, edge detection circuit, and test and control module. The ring
oscillator includes two transmitting triggers, a capturing trigger, a match path, and a
return path. The mat path and return path were divided into general delay array and
differential delay array, and each type’s order represents the mat path’sbufferdelaycanbe
fine-tuned precisely; another order presents the difference of buffer delays for different
specification buffers. The return protocol was calibrated to make the time delay of the
return path equal to one clock period. After calibrating the return and match path, connect
them together to constitute a ring, and one obstacle frequency was focused generating from
the ripple and the frequency. After removing the one clock period from the ripple and
obtaining a loop ripple period, the periodicity is the time delay of the critical path to be
measured. Edge detection circuit design is decisive in that the signal reached the same time
to the matching path and the critical path. Each edge detection circuit has a two-pin gate, a
two-pin OR gate, and a falling pole driving flip-flop. The whole purpose of the falling edge
work flip flop is to make output upper level. That is, the choice between two ends means
that the matching process of the critical path is completed. The control test is responsible
for controlling the control vectors of the match and return paths to complete the calibra-
tion process. In addition, it can crosstalk the oscillation period of the control test ring
fipple, and produce quality matrix and frequency data for further analysis and evaluation.
On-chip calibration is a combination of the above components, a highly accurate on-chip
calibration instrument for ICs that can precisely calibrate the ICs critical path block delay
based on aging evaluation. This concept promotes a precursor to measure the aging of IC
and maintain it.
4 EXPERIMENT AND RESULTS
In summary, the present invention includes a method and a testing circuit for evaluating the
aging durability of an integrated circuit and the on-chip calibration structure for simulation
and evaluation developed by the inventor. Testing was carried out in the HSPICE 2014
program to confirm the accuracy of the testing circuit in case of manufacturing uncertainty.
The 28-nm process library was used when simulating the testing, and the VCS was used to
perform the functional simulation of the test structure.
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To consider the manufacturing uncertainty, the Monte Carlo SPICE method in HSPICE
was used to further complicate the testing by introducing a variability model for 10% W(gate
width), 10% L (gate length), and 25% Vth ((threshold voltage of the MOS transistor). When
the on-chip calibration structure’s power supply voltage is 1.05V, the average time delay
difference of a single differential time delay unit is 2.760ps. After one year of aging, this
value increases to 3.874ps, approximately half of the test accuracy value for the critical path.
The delay-difference simulation structure of a single differential delay structure.
The on-chip calibration structure, designed by the inventor, is integrated into standard test
circuits (ITC benchmark) and 64-bit floating point and graphic units from an open-source
SPARC processor (OpenSPARC 2SPARC core). The insertion process is detailed in
Figure 1.
Initially, RTL design, synthesis, scan chain insertion, and layout generation are conducted
using EDA software for the original circuit. The durability assessment circuit is inserted into
the original circuit layout using IC Compiler software, and layout and wiring are performed
for the durability assessment structure. The total area and power consumption overhead
introduced by the on-chip calibration structure, after integration into the reference circuit,
are obtained and summarized in the table below. The on-chip calibration structure encom-
passes the overall footprint and the excess proportion of the circuit:
Furthermore, the procedure for assessment the aging durability of the integrated circuit
was verified using FPGA. The experimental procedure involved measuring the time delay of
a brand-new FPGA chip under different supply voltages (80C, 1.801V, 1.788V, and
1.775V). The path time delay distribution of different chips under different supply voltages.
By using the test data, the equivalent threshold voltage of the chip was calculated, allowing
for the prediction of the aging speed and the assessment of chip durability based on the initial
threshold voltage value.
Figure 1. A general process for simulating aging effects.
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Subsequently, an accelerated aging test was conducted on all the chips. The chips were
divided into two groups, and static aging and dynamic aging were performed under aging
conditions of 80C, 1.8V power supply voltage, and 9 hours of aging time. The time delay
value of the key path of the aged chips was retested. The actual aging speed of different
FPGAs was calculated using the aged time delay value and the initial time delay value. A
comparison of the predicted and actual burn-in rates for the chips. The experimental results
aligned with theoretical analysis.
In the static aging group, data from 93 chips provided effective test results. All the chips
underwent durability assessment based on the predicted threshold voltage values. Six chips
exhibited inconsistent predicted durability grades compared to the actual grade, resulting in
a durability assessment accuracy of 93.5%. In the dynamic aging group, data from 92 chips
provided effective test results, yielding a durability assessment accuracy rate of 95.7%.
Thus far, a detailed description has been provided for the assessment procedure of the
aging durability of the integrated circuit and the working principle of the on-chip calibration
structure, including its structure and operation. The durability assessment procedure and the
on-chip calibration structure offer several advantages:
(1) The procedure allows for assessment the aging durability of newly delivered integrated
circuits, with testing time comparable to vector-based testing procedures. It offers the
benefits of high testing speed and low testing cost.
(2) The provided aging durability assessment procedure is based on the time delay test result
of the critical path, which can accurately represent the actual aging speed of the inte-
grated circuit. It provides high prediction precision.
(3) The proposed path delay calibration structure calibrates the critical path time delay
during normal circuit operation, without change the original circuit structure, therefore
and exerts minimal influence on the original structure and timing of the integrated
circuit.
(4) The proposed path delay calibration structure were constructed by pure digital devices,
resulting in high calibration precision, fast feedback and response, and adding minimal
area and power overhead.
It has been verified by software simulation that the designed on-chip calibration structure
is feasible, and the area problem is discussed. Through the FPGA chip, the durability ver-
ification process of the calibration structure is successfully verified. Under the situation of
static aging, the accuracy is 93.5%, and the error rate reaches 95.7% for dynamic aging.
5 CONCLUSION
In conclusion, the research presents a robust assessment procedure for aging durability of
integrated circuits and the design and implementation of an on-chip structure for calibration.
This project has also illustrated the experimental results and analysis that demonstrate the
procedure and calibration structure’s effectiveness and advantages. The research has started
Table 1. Table comparing standard test circuits.
Standard Test Circuit b19 FGU Leon3s VGA-LCD
Number of Critical Paths to be Measured 32 51 39 21
Cost of Power Consumption (%) 1.62 0.87 1.73 1.53
Area Overhead (%) 1.25 0.67 0.78 0.92
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by verifying the procedure, using FPGA chips, measured the time delays of brand-new chips
under varying supply voltages. The characterization of path time delay distribution was
conducted to calculate the equivalent threshold voltage of the chips and predict the aging
speed and assess their durability according to the initial threshold voltage value. Accelerated
aging experimented on the actual chips provided data about the actual aging speed, then
analysed in comparison with the acrial prediction based on the initial threshold voltage
value. The various experimental results have indicated a good match between the theoretical
analysis and experimental findings, validation the durability assessment procedure.
Additionally, the on-chip calibration structure was designed and proven to not interfere with
normal operation while still measuring the time delay of the critical path. The designed
structure has a high precision with good speed in the response and remains minimal when
checking for power consumption. The on-chip structure has been successfully simulated
through software and further analysed in terms of area overhead on the circuit. These
mitigations have several advantages, tested, and validated the effectiveness of this. The
assessment procedure for aging durability of new delivered integrated circuits guaranteed
low testing time and cost since only a few critical path-time delay calibrations are required.
Moreover, the reliance of only vital path-time delay calibrations to estimate aging speed
ensures the h edge of the prediction on the aging speed. Moreover, the designed on-chip
calibration structure has proven to be practical and scalable. The structure verified digital
devices and no other significant resources overhead. This project addresses future works
studying the effect of roadkill path with asymmetrical effects, i.e. areas on the critical path
edges of the path, shall be proposed in the new version. Hence the research is contributed to
advancing integrated circuit durability assessment.
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