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Abstract

This paper presents a programmable digital filtering unit dedicated to operating with signals from infrared (IR) detection modules. The designed device is quite useful for increasing the signal-to-noise ratio due to the reduction in noise and interference from detector–amplifier circuits or external radiation sources. Moreover, the developed device is flexible due to the possibility of programming the desired filter types and their responses. In the circuit, an advanced field-programmable gate array FPGA chip was used to ensure an adequate number of resources that are necessary to implement an effective filtration process. The proposed circuity was assisted by a 32-bit microcontroller to perform controlling functions and could operate at frequency sampling of up to 40 MSa/s with 16-bit resolution. In addition, in our application, the sampling frequency decimation enabled obtaining relatively narrow passband characteristics also in the low frequency range. The filtered signal was available in real time at the digital-to-analog converter output. In the paper, we showed results of simulations and real measurements of filters implementation in the FPGA device. Moreover, we also presented a practical application of the proposed circuit in cooperation with an InAsSb mid-IR detector module, where its self-noise was effectively reduced. The presented device can be regarded as an attractive alternative to the lock-in technique, artificial intelligence algorithms, or wavelet transform in applications where their use is impossible or problematic. Comparing the presented device with the previous proposal, a higher signal-to-noise ratio improvement and wider bandwidth of operation were obtained.
Citation: Achtenberg, K.; Szplet, R.;
Bielecki, Z. Advanced, Real-Time
Programmable FPGA-Based Digital
Filtering Unit for IR Detection
Modules. Electronics 2024,13, 4449.
https://doi.org/10.3390/
electronics13224449
Academic Editor: Alexander Barkalov
Received: 8 October 2024
Revised: 8 November 2024
Accepted: 11 November 2024
Published: 13 November 2024
Copyright: © 2024 by the authors.
Licensee MDPI, Basel, Switzerland.
This article is an open access article
distributed under the terms and
conditions of the Creative Commons
Attribution (CC BY) license (https://
creativecommons.org/licenses/by/
4.0/).
Article
Advanced, Real-Time Programmable FPGA-Based Digital
Filtering Unit for IR Detection Modules
Krzysztof Achtenberg 1, * , Ryszard Szplet 2and Zbigniew Bielecki 1
1Institute of Optoelectronics, Military University of Technology, 2 Kaliskiego Str., 00-908 Warsaw, Poland
2Faculty of Electronics, Military University of Technology, 2 Kaliskiego Str., 00-908 Warsaw, Poland
*Correspondence: krzysztof.achtenberg@wat.edu.pl
Abstract: This paper presents a programmable digital filtering unit dedicated to operating with
signals from infrared (IR) detection modules. The designed device is quite useful for increasing the
signal-to-noise ratio due to the reduction in noise and interference from detector–amplifier circuits
or external radiation sources. Moreover, the developed device is flexible due to the possibility
of programming the desired filter types and their responses. In the circuit, an advanced field-
programmable gate array FPGA chip was used to ensure an adequate number of resources that are
necessary to implement an effective filtration process. The proposed circuity was assisted by a 32-bit
microcontroller to perform controlling functions and could operate at frequency sampling of up to
40 MSa/s with 16-bit resolution. In addition, in our application, the sampling frequency decimation
enabled obtaining relatively narrow passband characteristics also in the low frequency range. The
filtered signal was available in real time at the digital-to-analog converter output. In the paper, we
showed results of simulations and real measurements of filters implementation in the FPGA device.
Moreover, we also presented a practical application of the proposed circuit in cooperation with an
InAsSb mid-IR detector module, where its self-noise was effectively reduced. The presented device
can be regarded as an attractive alternative to the lock-in technique, artificial intelligence algorithms,
or wavelet transform in applications where their use is impossible or problematic. Comparing the
presented device with the previous proposal, a higher signal-to-noise ratio improvement and wider
bandwidth of operation were obtained.
Keywords: digital filter; FPGA; finite impulse response; FIR; infinite impulse response; IIR; IR
detector; digital signal processing; DSP; IR detection module
1. Introduction
Field-programmable gate array (FPGA) devices have become a popular and effective
platform for digital signal processing (DSP) implementations [
1
,
2
]. These specific and
flexible architectures of integrated circuit (IC) resources can be used in a wide range of
applications like image processing, neural network systems, measurement instrumentation,
or fast acquisitions [
3
5
]. Furthermore, last year’s effective use of FPGAs in quantum
systems and nuclear physics was also observed [
6
]. The high popularity of this type of IC
is determined primarily by the possibility of simple adjustment of the desired function via
proper configuration. The prepared hardware description language (HDL) code determines
the setting of internal connections between individual logic elements [
7
]. In this way,
building complete, advanced digital systems is achievable. Using FPGAs, it is also possible
to obtain a substitute for the application-specific integrated circuit (ASIC) only by preparing
the appropriate HDL code. This allows for lower prototyping or production costs than a
typical ASIC [
8
]. The main limitation of such a method is that FPGA ICs are typically not
equipped with advanced analog blocks, and external electronic elements are necessary for
specific applications. In some advanced FPGA devices, built-in simple analog-to-digital
converters (ADCs) can be found [
9
]. In the literature, we can find various functionalities
Electronics 2024,13, 4449. https://doi.org/10.3390/electronics13224449 https://www.mdpi.com/journal/electronics
Electronics 2024,13, 4449 2 of 19
implemented using FPGAs: filtering, precision time interval measurement, arithmetic or
cryptographic co-processor, fast transceivers or receivers, and many others [
10
13
]. This is
mainly because FPGA systems are more efficient than typical processors. In many cases,
they can perform complex mathematical operations in a one clock cycle. Authors in [
10
]
presented the application of FPGA-based filtering to reduce the influence of noise and
interferences in space satellite systems. In [
13
], the digital filter was designed to denoise
electroencephalography signals from unwanted components.
Infrared (IR) photodetectors are devices used to convert infrared radiation energy
into an electrical signal. Typically, a distinction is made between thermal and photonic
groups depending on the physical phenomenon used (heating of a photosensitive element
or generation of photocurrent due to the specific interaction of photons with electrons) [
14
].
The vast majority of IR detectors use semiconductor materials as a photosensitive element.
For this reason, there has been significant development in their materials’ engineering tech-
nology. Appropriate selection of material, doping, and architecture enables the construction
of detectors with various parameters, including the operating spectral range [15].
Meaningful progress in recent decades has led to the development of detectors operat-
ing from short-wave IR (SWIR) to very-long-wave IR (VLWIR). The most popular semicon-
ductor materials used for their production include mercury cadmium telluride (HgCdTe,
MCT), indium arsenide (InAs), indium antimonide (InSb), indium arsenide antimonide
(InAsSb), indium gallium arsenide (InGaAs), and also silicon (Si) [
16
18
]. In contrast
to these materials, graphene is a promising optoelectronic material for ultra-broadband
photodetectors due to its gapless band structure [19].
Directly using the signal from an IR detector is problematic due to its typical small
value. Due to this fact, a specially designed amplifier is usually necessary to convert it into
higher measurable amplitude values. The most popular of them is the transimpedance
amplifier (TIA), but in some cases, voltage amplifiers (VAs) are also used [
20
]. The specific
model of the amplifier depends on the type of its operation: photovoltaic or photoconduc-
tive mode. Several parameters can characterize each detector. The most important of them
are normalized detectivity (D*), current or voltage responsivity (R
i
/R
V
), noise equivalent
power (NEP), and time constant (
τ
). These parameters depend on the temperature and
bias voltage applied to the detector. The main limitation of IR detector operability is the
noise generation phenomenon because of its direct influence on D* and NEP values. The
IR detector noise power spectrum density (PSD) usually rises along with the bias and
temperature, so the cooling improves its parameters [
21
]. However, in order to obtain
appropriate frequency parameters for the system related to the short
τ
, they require the use
of an appropriate bias and the adequate type of amplifier, which unfortunately leads to an
increase in noise in the output signal. This applies primarily to low-frequency noise of the
1/ftype [
22
]. For this reason, certain procedures are usually observed to reduce the impact
of noise on the parameters of the target system. One of them is the lock-in technique or
appropriate filtration that can be performed in analog or digital processing traces [23,24].
IR detectors have found various effective applications in industry, consumers, and the
military [
25
27
]. They can be found in temperature monitoring, communication, medical,
security, and imaging systems [
28
31
]. In all applications, noise led to some limitations and
parameters deteriorating.
DSP is one of the most effective techniques of signal manipulation. Appropriate
algorithms enable the implementation of several functions, like converting, transforming,
filtering, compression, and many others [
32
,
33
]. Some functions can also be provided in
both time and frequency domains. In many cases, e.g., regarding filtration, the efficiency
of the DSP system significantly exceeds the analog solutions, due to more flexibility in
parameter adjusting. DSP systems can be based on processors (CPU), microcontrollers
(
µ
C), system-on-chip (SoC), dedicated digital signal processors, or FPGAs [
34
36
]. Some-
times, application-specific ICs (ASICs) are equipped with special modules dedicated to
implementing DSP functions, e.g., Fast Fourier Transform (FFT) [37].
Electronics 2024,13, 4449 3 of 19
This work combined the few above-described devices and techniques to construct a
specialized unit that can improve the signal-to-noise ratio (SNR). The high-performance
digital filter was implemented in an advanced FPGA IC using HDL to reject unwanted
noises and external radiation signals from the output of the IR detection module.
The presented unit can be programmed to obtain the necessary form (low-pass, band-
pass, etc.) and characteristics of the filter (e.g., frequency or phase response). Thanks to
the large number of resources in the FPGA that can be used to construct it, an advanced,
effective filtering unit capable of suppressing unwanted signals at a level exceeding several
dozen dB can be obtained.
In the paper, we presented the hardware construction of the circuit, a result of the
simulations of the example filters, and its practical implementation. The well-known
techniques and parts were combined to construct an advanced FPGA-based system for
real-time measurements, where high-order filters can be implemented. Moreover, we
also conducted a practical experiment with the InAsSb mid-wave IR (MWIR) detection
module, where noise is quite problematic when operating with weak signals. The obtained
performances are significantly better than previous work [
38
]. The advantage of real-time
operation can be especially useful in systems where quick reaction is necessary.
2. Hardware and Methods
2.1. Hardware Platform
Each DSP system is composed of an appropriate combination of hardware and soft-
ware. Operating with analog signals usually requires the application of data converters,
like analog-to-digital converters and/or digital-to-analog converters (DACs). The selection
of their specific properties depends strictly on the target application. Analog front-ends
are also often used in signal paths to prepare input–output signals by adapting them to
converters (ADCs, DACs). The generalized hardware block diagram of a typical DSP
system (that can be used for filtering) containing an ADC and DAC is presented in Figure 1.
Electronics 2024, 13, x FOR PEER REVIEW 3 of 19
Sometimes, application-specific ICs (ASICs) are equipped with special modules dedicated
to implementing DSP functions, e.g., Fast Fourier Transform (FFT) [37].
This work combined the few above-described devices and techniques to construct
a specialized unit that can improve the signal-to-noise ratio (SNR). The high-performance
digital lter was implemented in an advanced FPGA IC using HDL to reject unwanted
noises and external radiation signals from the output of the IR detection module.
The presented unit can be programmed to obtain the necessary form (low-pass, band-
pass, etc.) and characteristics of the lter (e.g., frequency or phase response). Thanks to
the large number of resources in the FPGA that can be used to construct it, an advanced,
eective ltering unit capable of suppressing unwanted signals at a level exceeding sev-
eral dozen dB can be obtained.
In the paper, we presented the hardware construction of the circuit, a result of the
simulations of the example lters, and its practical implementation. The well-known tech-
niques and parts were combined to construct an advanced FPGA-based system for real-
time measurements, where high-order lters can be implemented. Moreover, we also con-
ducted a practical experiment with the InAsSb mid-wave IR (MWIR) detection module,
where noise is quite problematic when operating with weak signals. The obtained perfor-
mances are signicantly beer than previous work [38]. The advantage of real-time oper-
ation can be especially useful in systems where quick reaction is necessary.
2. Hardware and Methods
2.1. Hardware Platform
Each DSP system is composed of an appropriate combination of hardware and soft-
ware. Operating with analog signals usually requires the application of data converters,
like analog-to-digital converters and/or digital-to-analog converters (DACs). The selection
of their specic properties depends strictly on the target application. Analog front-ends
are also often used in signal paths to prepare inputoutput signals by adapting them to
converters (ADCs, DACs). The generalized hardware block diagram of a typical DSP sys-
tem (that can be used for ltering) containing an ADC and DAC is presented in Figure 1.
DSP block
(ex. FPGA or
CPU)
Analog
front-end
Analog
front-end
Signal
input
Signal
output
ADC DAC
Figure 1. Generalized hardware block diagram of typical DSP system with ADC and DAC that can
be used to implement digital lter.
The analog input signal is applied to the analog front-end. This block is usually based
on properly selected operational amplifiers, which adjust the signal to the ADC input. It
can be amplication, aenuation, ltering, or a change to a dierential signal to drive ADC
inputs properly. The sampled and digitized data are sent to the DSP block, where the
adequate function is implemented. A processed digital signal can be read from this block
or converted to the analog domain via DAC. At its output, an analog front-end can also be
applied. It can perform similar functions, like in the case of the ADC front-end.
Figure 2 presents the block diagram of the digital ltering unit we developed in our
work. The less important elements were intentionally omied in this gure.
The input signal was connected to the anti-aliasing low-pass lter (LPF) to reject fre-
quencies above half of the sampling frequency. This lter was needed to ensure it operated
by the Nyquist sampling theorem and avoided the aliasing phenomenon [39]. In our cir-
cuit, we used the two stages of the SallenKey conguration with elements calculated to
obtain Bessel-type characteristics [40]. The lter was characterized by a at response to
about 1 MHz with aenuation less than 0.1 dB, whereas its cut-off (−3 dB) frequency
equaled 4.3 MHz. The −10 dB signal aenuation occurred at a frequency of 8.1 MHz. The
oscillations observed in step response were reduced thanks to the Bessel character.
Figure 1. Generalized hardware block diagram of typical DSP system with ADC and DAC that can
be used to implement digital filter.
The analog input signal is applied to the analog front-end. This block is usually based
on properly selected operational amplifiers, which adjust the signal to the ADC input. It
can be amplification, attenuation, filtering, or a change to a differential signal to drive
ADC inputs properly. The sampled and digitized data are sent to the DSP block, where the
adequate function is implemented. A processed digital signal can be read from this block
or converted to the analog domain via DAC. At its output, an analog front-end can also be
applied. It can perform similar functions, like in the case of the ADC front-end.
Figure 2presents the block diagram of the digital filtering unit we developed in our
work. The less important elements were intentionally omitted in this figure.
The input signal was connected to the anti-aliasing low-pass filter (LPF) to reject
frequencies above half of the sampling frequency. This filter was needed to ensure it
operated by the Nyquist sampling theorem and avoided the aliasing phenomenon [
39
]. In
our circuit, we used the two stages of the Sallen–Key configuration with elements calculated
to obtain Bessel-type characteristics [
40
]. The filter was characterized by a flat response
to about 1 MHz with attenuation less than 0.1 dB, whereas its cut-off (
3 dB) frequency
equaled 4.3 MHz. The
10 dB signal attenuation occurred at a frequency of 8.1 MHz. The
oscillations observed in step response were reduced thanks to the Bessel character.
Electronics 2024,13, 4449 4 of 19
Electronics 2024, 13, x FOR PEER REVIEW 4 of 19
Pipel ine
ADC
LDO
LT1763
3.3 V
FPGA
KIN TEX 7
XC7K325T
(28 nm)
DATA [15:0]
CLK
SDA TA
SCLK
SEN
RES ET
ADC
ADS5560
DAC
LTC1668
DATA [15:0]
CLK
AV
DD
DR
VDD
LA DCOM
V
out
JTAG
V
SS
V
DD
5 V -5 V
µC
STM32H750
DATA [15:0]
CLK
SCLK
SDA TA
UART to PC
LDO
LT1763
3.3 V
40 MHz
XTAL
gen.
Ext. gen.
CLK
LPF and
single-e nded
to
dif fer ential
converter
V
in
PC
V
CM
V
CM
bias
cir cu it
SEN
RES ET
Differential
current out to
single voltage
converter and
LPF
REF OUT
I
REFI N
R
SET
LDO
LT1763
LDO
LT3094
INP
INM
I
OUTA
I
OUTB
1.5 V
Figure 2. The block diagram of the hardware platform for the digital ltering unit.
The 16-bit CMOS parallel interface was used to exchange data with the FPGA. ADC
can be clocked with a constant frequency of 40 MHz from a crystal generator or an exter-
nally connected generator using a dedicated SMA connector. According to the datasheet,
this ADC had a high SNR of 84 dBFS, adjustable ne gain, internal voltage reference, and
low-frequency suppression mode [41]. It was enclosed in a 48-VQFN surface-mount pack-
age. The internal registers of ADS5560 could be controlled via serial interface lines (RE-
SET, SEN, SCLK, SDATA) using µC (FPGA was working only as a simple signal bridge).
They were responsible for the gain, output data interface, format, and sampling frequency
range. In the case of a sampling frequency 25 MSa/s, the specic register bit needed be
set. Both the ADC and dierential ampliers on the front end operated with a common-
mode voltage of VCM = 1.5 V. The main DSP operations were performed on the Xilinx se-
ries-7 KINTEX XC7K325T FPGA device [42]. The main device properties regarding the
available resources are listed in Table 1. In this table, the properties of Xilinx ARTIX-7
XC7A35T used in similar previous work [38] were also included for comparison.
Table 1. Resources of XC7K325T and XC7A35T.
Resource Name
XC7K325T
XC7A35T Used in [38]
Logic Cells
326,080
33,280
Slices
50,950
5200
DSP Slices
840
90
Memory
16,020
1800
Max. I/O Pins
500
250
XC7K325T was characterized by about ten times more logic resources and functional
blocks than XC7A35T. Regarding DSP-based ltering operations, the number of DSP slices
and logic cells dened the nal possibilities. This is because most operations were based
on multiplication, summation, or accumulation. In the FPGA, typically specialized DSP
slices (highlighted in Table 1) were dedicated to this operation, i.e., DSP48 in the KINTEX-
7 family of FPGAs.
The digitally processed signal was sent to the DAC via a parallel interface. In our
circuit, we used a 16-bit LTC1668 DAC. Its dierential current outputs could be updated
at a maximum 50 MSa/s rate. It was characterized by high spectral purity (87 dB SFDR at
fout = 1 MHz), a low 5 pV-s glitch impulse, and 20 ns of seling time. The DAC chip was
enclosed in a 28-pin SSOP package. It could operate with TTL/CMOS 3.3 V or 5 V input
signals [43]. Output differential current signals were converted into single-ended using an
I-V converter based on a high-speed LT1819 op-amp. Then, the single-ended voltage sig-
nal was ltered using the same lter type as the one used for the ADC input. The role of
Figure 2. The block diagram of the hardware platform for the digital filtering unit.
The 16-bit CMOS parallel interface was used to exchange data with the FPGA. ADC
can be clocked with a constant frequency of 40 MHz from a crystal generator or an externally
connected generator using a dedicated SMA connector. According to the datasheet, this
ADC had a high SNR of 84 dBFS, adjustable fine gain, internal voltage reference, and low-
frequency suppression mode [
41
]. It was enclosed in a 48-VQFN surface-mount package.
The internal registers of ADS5560 could be controlled via serial interface lines (RESET,
SEN, SCLK, SDATA) using
µ
C (FPGA was working only as a simple signal bridge). They
were responsible for the gain, output data interface, format, and sampling frequency range.
In the case of a sampling frequency
25 MSa/s, the specific register bit needed be set.
Both the ADC and differential amplifiers on the front end operated with a common-mode
voltage of V
CM
= 1.5 V. The main DSP operations were performed on the Xilinx series-7
KINTEX XC7K325T FPGA device [
42
]. The main device properties regarding the available
resources are listed in Table 1. In this table, the properties of Xilinx ARTIX-7 XC7A35T used
in similar previous work [38] were also included for comparison.
Table 1. Resources of XC7K325T and XC7A35T.
Resource Name XC7K325T XC7A35T Used in [38]
Logic Cells 326,080 33,280
Slices 50,950 5200
DSP Slices 840 90
Memory 16,020 1800
Max. I/O Pins 500 250
XC7K325T was characterized by about ten times more logic resources and functional
blocks than XC7A35T. Regarding DSP-based filtering operations, the number of DSP slices
and logic cells defined the final possibilities. This is because most operations were based
on multiplication, summation, or accumulation. In the FPGA, typically specialized DSP
slices (highlighted in Table 1) were dedicated to this operation, i.e., DSP48 in the KINTEX-7
family of FPGAs.
The digitally processed signal was sent to the DAC via a parallel interface. In our
circuit, we used a 16-bit LTC1668 DAC. Its differential current outputs could be updated at
a maximum 50 MSa/s rate. It was characterized by high spectral purity (87 dB SFDR at
f
out
= 1 MHz), a low 5 pV-s glitch impulse, and 20 ns of settling time. The DAC chip was
enclosed in a 28-pin SSOP package. It could operate with TTL/CMOS 3.3 V or 5 V input
signals [
43
]. Output differential current signals were converted into single-ended using an
I-V converter based on a high-speed LT1819 op-amp. Then, the single-ended voltage signal
was filtered using the same filter type as the one used for the ADC input. The role of the
Electronics 2024,13, 4449 5 of 19
DAC output filter was to reject clock and the above Nyquist frequency signal components.
It also reduced the effect of zero-order keeping (visible in the time domain as steps) and
was sometimes named a “restoration” filter [44].
The FPGA and ADC main features were managed using the STMicroelectronics
STM32H750 microcontroller. It could also be further used to extract filtered data from
FPGA internal memory registers. A universal asynchronous receiver–transceiver interface
was applied to establish a connection with the PC. For practical realization, the overall
unit was divided into three printed circuit boards (PCBs) boards, namely ADC/DAC,
FPGA, and
µ
C. The supply and ground planes in the ADC/DAC 4-layer PCB were divided
into digital and analog parts to avoid interferences. The required voltages were provided
from low-noise LT1763 and LT3094 low-dropout (LDO) regulators. In the case of the
FPGA and
µ
C, we used the evaluation core boards. The
µ
C module daughterboard
was also projected to ensure proper header connectors with the FPGA evaluation board.
Analog input and output signals could be connected via SMA connectors. A photo of the
developed hardware platform for digital filtering is presented in Figure 3. In this figure,
some additional connectors are also visible (i.e., bypassing analog front-end LPFs and
additional clocks).
Electronics 2024, 13, x FOR PEER REVIEW 5 of 19
the DAC output lter was to reject clock and the above Nyquist frequency signal compo-
nents. It also reduced the eect of zero-order keeping (visible in the time domain as steps)
and was sometimes named a restoration lter [44].
The FPGA and ADC main features were managed using the STMicroelectronics
STM32H750 microcontroller. It could also be further used to extract ltered data from
FPGA internal memory registers. A universal asynchronous receivertransceiver interface
was applied to establish a connection with the PC. For practical realization, the overall
unit was divided into three printed circuit boards (PCBs) boards, namely ADC/DAC,
FPGA, and µC. The supply and ground planes in the ADC/DAC 4-layer PCB were divided
into digital and analog parts to avoid interferences. The required voltages were provided
from low-noise LT1763 and LT3094 low-dropout (LDO) regulators. In the case of the
FPGA and µC, we used the evaluation core boards. The µC module daughterboard was
also projected to ensure proper header connectors with the FPGA evaluation board. Ana-
log input and output signals could be connected via SMA connectors. A photo of the de-
veloped hardware platform for digital ltering is presented in Figure 3. In this gure,
some additional connectors are also visible (i.e., bypassing analog front-end LPFs and ad-
ditional clocks).
Figure 3. The photo of the hardware platform developed for the digital ltering unit.
Inside the FPGA, we applied a few blocks that were responsible for dierent func-
tions. The input ADC data in two complement codes were connected to the decimator
block. It was responsible for data decimation to obtain a lower sampling frequency than
an ADC clock. This was especially important for sampling rates below 1 MSa/s because,
according to the ADS5560 datasheet, it can properly operate only above this rate. The dec-
imator can also be set to a decimation factor of 1 to bypass this operation. Then, the data
with the needed rate were applied to the lter core that performed the overall ltering
operation. An output coding converter was necessary to convert two complement codes
into a straight binary, which was required by LTC1668 DAC inputs. Inside the FPGA, the
additional memory block can also be applied to enable the possibility of extracting ltered
data to µC. The lter architecture and coefficients were constant and stored inside the lter
core block. A dedicated VIVADO design environment was used to prepare, synthesize,
and implement Very High-Speed Integrated Circuit Hardware Description Language
(VHDL) codes in FPGA. The block diagram of the functionality of the internal module
implementation in the FPGA device is presented in Figure 4.
Figure 3. The photo of the hardware platform developed for the digital filtering unit.
Inside the FPGA, we applied a few blocks that were responsible for different functions.
The input ADC data in two complement codes were connected to the decimator block. It
was responsible for data decimation to obtain a lower sampling frequency than an ADC
clock. This was especially important for sampling rates below 1 MSa/s because, according
to the ADS5560 datasheet, it can properly operate only above this rate. The decimator can
also be set to a decimation factor of 1 to bypass this operation. Then, the data with the
needed rate were applied to the filter core that performed the overall filtering operation.
An output coding converter was necessary to convert two complement codes into a straight
binary, which was required by LTC1668 DAC inputs. Inside the FPGA, the additional
memory block can also be applied to enable the possibility of extracting filtered data to
µ
C.
The filter architecture and coefficients were constant and stored inside the filter core block.
A dedicated VIVADO design environment was used to prepare, synthesize, and implement
Very High-Speed Integrated Circuit Hardware Description Language (VHDL) codes in
FPGA. The block diagram of the functionality of the internal module implementation in
the FPGA device is presented in Figure 4.
Electronics 2024,13, 4449 6 of 19
Electronics 2024, 13, x FOR PEER REVIEW 6 of 19
Dec ima tor Filte r
core
Optional
memory
Coding
converter
ADC da ta DAC da ta
Command
driver
to µC
FPGA
Figure 4. Block diagram of the internal functional module implemented in the FPGA device.
2.2. Digital Filters
Generally, the lter core can be implemented in various forms. Regarding impulse
response length, digital lters can be divided into two categories: nite impulse response
(FIR) and innite impulse response (IIR) [45]. Moreover, its architecture types can also be
dierent, like direct forms (i.e., biquad) or transformed forms [46]. All of their properties
have an inuence on the nal behavior and implementation procedure. The example ar-
chitectures of FIR (direct form) and IIR (direct form I-biquad) in the form of schematic
blocks are presented in Figure 5.
x[n] x[n-1] x[n-2] x[n-q]
Σ Σ Σ
y[n]
z-1 z-1 z-1
b
0
b
1
b
2
b
q
z
-1
z
-1
Σ
x[n]
z
-1
z
-1
a
1
a
2
a
0
y[n]
-b
1
-b
2
z
-1
z
-1
a
p
-b
q
(a)
Figure 5. Example schematic block diagrams of direct form FIR (a) and direct form I-biquad IIR (b)
lter implementations. Square blocks are delayers, and triangular blocks are multipliers by con-
stants.
The FIR structure was composed of a q-stage delay line with q + 1 taps. The output
data from unit delays were multiplied by the bi coecient (impulse response). All multi-
plications were summed to produce an output result. It was a dierent situation was in
the case of the IIR, where the output y[n] sample was given to create a feedback loop con-
nected to the sum block. Such an operation created a situation of innite impulse response
because each output sample was looped back and had some inuence on the next output
signal sample.
When deciding between the FIR and IIR, parameters related to the phase response
and resource availability in the target system are usually taken into account. Table 2 sum-
marizes the main properties of both lter types.
Figure 4. Block diagram of the internal functional module implemented in the FPGA device.
2.2. Digital Filters
Generally, the filter core can be implemented in various forms. Regarding impulse
response length, digital filters can be divided into two categories: finite impulse response
(FIR) and infinite impulse response (IIR) [
45
]. Moreover, its architecture types can also be
different, like direct forms (i.e., biquad) or transformed forms [
46
]. All of their properties
have an influence on the final behavior and implementation procedure. The example
architectures of FIR (direct form) and IIR (direct form I-biquad) in the form of schematic
blocks are presented in Figure 5.
Electronics 2024, 13, x FOR PEER REVIEW 6 of 19
Dec ima tor Filte r
core
Optional
memory
Coding
converter
ADC da ta DAC da ta
Command
driver
to µC
FPGA
Figure 4. Block diagram of the internal functional module implemented in the FPGA device.
2.2. Digital Filters
Generally, the lter core can be implemented in various forms. Regarding impulse
response length, digital lters can be divided into two categories: nite impulse response
(FIR) and innite impulse response (IIR) [45]. Moreover, its architecture types can also be
dierent, like direct forms (i.e., biquad) or transformed forms [46]. All of their properties
have an inuence on the nal behavior and implementation procedure. The example ar-
chitectures of FIR (direct form) and IIR (direct form I-biquad) in the form of schematic
blocks are presented in Figure 5.
x[n] x[n-1] x[n-2] x[n-q]
Σ Σ Σ
y[n]
z-1 z-1 z-1
b
0
b
1
b
2
b
q
z
-1
z
-1
Σ
x[n]
z
-1
z
-1
a
1
a
2
a
0
y[n]
-b
1
-b
2
z
-1
z
-1
a
p
-b
q
(a)
(b)
Figure 5. Example schematic block diagrams of direct form FIR (a) and direct form I-biquad IIR (b)
lter implementations. Square blocks are delayers, and triangular blocks are multipliers by con-
stants.
The FIR structure was composed of a q-stage delay line with q + 1 taps. The output
data from unit delays were multiplied by the bi coecient (impulse response). All multi-
plications were summed to produce an output result. It was a dierent situation was in
the case of the IIR, where the output y[n] sample was given to create a feedback loop con-
nected to the sum block. Such an operation created a situation of innite impulse response
because each output sample was looped back and had some inuence on the next output
signal sample.
When deciding between the FIR and IIR, parameters related to the phase response
and resource availability in the target system are usually taken into account. Table 2 sum-
marizes the main properties of both lter types.
Figure 5. Example schematic block diagrams of direct form FIR (a) and direct form I-biquad IIR (b) fil-
ter implementations. Square blocks are delayers, and triangular blocks are multipliers by constants.
The FIR structure was composed of a q-stage delay line with q+ 1 taps. The output
data from unit delays were multiplied by the b
i
coefficient (impulse response). All mul-
tiplications were summed to produce an output result. It was a different situation was
in the case of the IIR, where the output y[n] sample was given to create a feedback loop
connected to the sum block. Such an operation created a situation of infinite impulse
response because each output sample was looped back and had some influence on the next
output signal sample.
When deciding between the FIR and IIR, parameters related to the phase response and
resource availability in the target system are usually taken into account. Table 2summarizes
the main properties of both filter types.
Electronics 2024,13, 4449 7 of 19
Table 2. Main properties of FIR and IIR filters.
Property FIR IIR
Implementation cost High Low
Stability Stable Can be unstable
Latency High Low
Phase response Linear Non-linear
Analog equivalent No Yes
Customization and
implementation
Easy customization and
implementation
More difficult customization
and implementation
Analyzing the properties of both filters, it should be highlighted that the main dif-
ferences included implementation costs, phase response, and stability. Comparing im-
plementation costs, it can be stated that regarding similar filters, the IIR filters required
fewer hardware resources than the FIR. This is caused mainly by less multiplications being
needed by the IIR architecture.
2.3. Filter Core Design, Simulation of Its Characteristics, and HDL Code Preparing for FPGA
The overall behavior of the filtering unit depends on the filter core and sampling
frequency. From a mathematical point of view, digital filtering uses the operation of
convolution of the input signal with the filter impulse response. Assuming operation on
the input discrete signal x[n], the output signal y[n] of an FIR filter can be described as
follows [47]:
y[n]=q
i=0bi·x[ni], (1)
where qis the filter order, and b
i
is the impulse response value at the i-th instant for
0iq
of a q-th-order filter. For the direct form of the FIR, b
i
is also a filter coefficient. In the case
of the IIR, such an equation takes the following form:
y[n]=1
a0hp
j=1aj·y[nj]+q
i=0bi·x[ni]i(2)
Our work used the MATLAB environment to design, simulate, and generate the HDL
code. The Filter Designer Tool (FDT) built-in MATLAB R2024a software can prepare an
overall filter core HDL code depending on the requirements. Using FDT, we can manage
filter properties like type (low-pass, band-pass, etc.), response, design method, order,
frequency, and magnitude responses. The calculated coefficients must be quantized and
adapted to the desired representations since the FDT operates on floating-point numbers in
either double-precision or single-precision format. In the case of the FPGA, we used the
FDT built-in function of quantizing into 16-bit fixed-point representations. As the number
of different types of filters that can be implemented is quite enormous, we can present
only a few examples without a thorough analysis of individual characteristics and design
methods in this paper. The fundamentals of Butterworth, Bessel, Chebyshev, or elliptic
filters can be found in [
48
,
49
]. The considerations about design methods like equiripple
or windowing are described in [
50
,
51
]. The main differences between these filters are
related to some compromise between the passband and stopband behavior. For example,
the Chebyshev filter is characterized by high attenuation in the stopband (in comparison
with others) at the cost of oscillations of gain in the passband and also after step response.
The Bessel type is free of these disadvantages at the expense of weaker attenuation in
the stopband.
In the case of our application with the IR detection module, narrow-band filtering
can most effectively improve the SNR by attenuating 1/fand wide-band white noises.
Due to this fact, we decided to present the results focusing on band-pass filters. The
example results of simulations in the FDT of FIR windowed-sinc band-pass filters (BPFs) for
different window types are presented in Figure 6. In this figure, the frequency (Figure 6a),
phase (Figure 6b), impulse (Figure 6c), and step (Figure 6d) responses were simulated
Electronics 2024,13, 4449 8 of 19
for a normalized 840-order (like the number of DSP blocks in the XC7K325T) filter. The
passband was set from 0.01 to 0.02 of normalized frequency as some compromise between
the narrowest possible band without significant attenuation at its center frequency.
Electronics 2024, 13, x FOR PEER REVIEW 8 of 19
normalized 840-order (like the number of DSP blocks in the XC7K325T) lter. The pass-
band was set from 0.01 to 0.02 of normalized frequency as some compromise between the
narrowest possible band without signicant aenuation at its center frequency.
(a)
(b)
(c)
(d)
Figure 6. Frequency (a), phase (b), impulse (c), and step (d) responses for normalized 840-order
windowed-sinc lter. The passband was set from 0.01 to 0.02 of normalized frequency.
Each of the applied windows caused a change in resulting characteristics. The highest
aenuation in the stopband was observed in the case of the Blackman window. This ex-
plains the fact that this type of windowing is typically used. The lower aenuation in the
stopband was observed for Kaiser and BarleHanning windows at the expense of steeper
slopes near the passband. The BarleHanning window was characterized by the weakest
oscillations at stopband frequencies and other phase responses (without accumulation).
For other types of windows, the accumulation oscillating around a certain level was ob-
served before and after the passband. In the passband range, the phase was linear, with
some delay observed for all windows. Analyzing impulse and step responses, the sinc-like
characteristics with slight differences were observed (the higher amplitude for Kaiser). In
the case of pulsed signals, some types of lters can lead to signicant distortions, includ-
ing oscillations visible in the step response characteristics.
As we mentioned before, the performance of the implemented digital lter depends
on the number of available resources. In practice, it is the number of multiplications and
summations that can be performed in the required time. It must be highlighted that, the-
oretically, such a lter core can also operate at a rate other than sampling frequency. Then,