Efficient Power Conditioning: Enhancing Electric Supply for Small Satellite Missions

Abstract

Electric power supply (EPS) is the heart of any aerospace mission and plays an important role in improving the performance and service lifetime of spacecraft. It generates, converts, stores, and distributes power to different voltage levels. The EPS is composed of solar panels, a power conditioning unit (PCU), batteries, and a power distribution unit (PDU). This paper describes the design and analysis of an efficient power conditioning system for a CubeSat standard small satellite. For this purpose, the aim of this paper is to propose a two-input maximum power point tracker (MPPT)-based interleaved boost converter. The design copes with the fact that when a satellite revolves around the Earth, a single panel or at most two panels face solar radiation at different angles. In order to extract maximum power from the panels, the designed converter drives the solar panels at the maximum power point (MPP). A small signal model is drawn for the converter, and the closed-loop gain of the converter is analyzed using a Bode diagram. To improve the phase margin and gain, a PID compensator is designed and added to the closed loop of the converter. Finally, the performance of the proposed converter is validated by the simulation results.

Full text

Citation: Khan, S.A.; Ali, A.; Tahir, M.;
Tao, Z. Efficient Power Conditioning:
Enhancing Electric Supply for Small
Satellite Missions. Aerospace 2024,11,
920. https://doi.org/10.3390/
aerospace11110920
Academic Editor: Mikhail
Ovchinnikov
Received: 7 September 2024
Revised: 24 October 2024
Accepted: 25 October 2024
Published: 8 November 2024
Copyright: © 2024 by the authors.
Licensee MDPI, Basel, Switzerland.
This article is an open access article
distributed under the terms and
conditions of the Creative Commons
Attribution (CC BY) license (https://
creativecommons.org/licenses/by/
4.0/).
Article
Efficient Power Conditioning: Enhancing Electric Supply for
Small Satellite Missions
Shoaib Ahmed Khan 1, Anwar Ali 2, * , Mustafa Tahir 3and Zou Tao 1
1College of Electrical and Mechanical Engineering, Guangzhou University, Guangzhou 510006, China;
shoaib.ahmed@zju.edu.cn (S.A.K.); tzou@gzhu.edu.cn (Z.T.)
2Department of Electronic and Electrical Engineering, Swansea University, Swansea SA1 8EN, UK
3College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China; mustafatahir@zju.edu.cn
*Correspondence: anwar.ali@swansea.ac.uk
Abstract: Electric power supply (EPS) is the heart of any aerospace mission and plays an important
role in improving the performance and service lifetime of spacecraft. It generates, converts, stores,
and distributes power to different voltage levels. The EPS is composed of solar panels, a power
conditioning unit (PCU), batteries, and a power distribution unit (PDU). This paper describes the
design and analysis of an efficient power conditioning system for a CubeSat standard small satellite.
For this purpose, the aim of this paper is to propose a two-input maximum power point tracker
(MPPT)-based interleaved boost converter. The design copes with the fact that when a satellite
revolves around the Earth, a single panel or at most two panels face solar radiation at different
angles. In order to extract maximum power from the panels, the designed converter drives the solar
panels at the maximum power point (MPP). A small signal model is drawn for the converter, and the
closed-loop gain of the converter is analyzed using a Bode diagram. To improve the phase margin
and gain, a PID compensator is designed and added to the closed loop of the converter. Finally, the
performance of the proposed converter is validated by the simulation results.
Keywords: two-input interleaved converter; MPPT; Bode diagram; small signal model; small satellites
1. Introduction
Satellites have always been considered to be an extremely expensive and risky busi-
ness that not only requires extensive knowledge and expertise in the field but also a huge
budget [
1
]. Consequently, space exploration has only been accessible to countries that have
had the required financial and sophisticated technological resources [
2
]. The responsibility
of carrying out space missions was mainly under the jurisdiction of powerful space agen-
cies such as NASA, ESA, CNSA, JAXA, ROSCOSMOS, and ISRO. These space research
organizations, being governmental institutions, carried out societal functions such as being
carriers of knowledge and education and promoting advanced technology [
3
]. With the
passage of time, many universities and SMEs (Small/Medium Enterprises) emerged and
entered this market with the objective of organizing space missions at a fraction of the cost,
accepting the failure risk in space exploration due to cheaper production and shorter devel-
opment periods [
4
]. At present, several private companies, such as SpaceX, Rocketplane
Kistler, Blue origin orbital, and Sierra Nevada space systems Sciences Corp., are providing
Commercial Orbital Transportation Services, which further decrease the cumulative cost.
The latest result of their efforts is the CubeSat concept: a small satellite with cube units with
dimensions of 10 cm
3
, built using COTS components [
5
–
7
]. Low-cost design techniques
played an important role in the aerospace market’s growth in the previous decade, and
they can still play a major part in future developments [8–10].
The primary functions of a spacecraft’s EPS are the proper conditioning and transmis-
sion of the generated power from the energy source to the batteries and subsystems [
11
,
12
].
The EPS is one of the integral parts of a satellite and performs power harvesting, power
Aerospace 2024,11, 920. https://doi.org/10.3390/aerospace11110920 https://www.mdpi.com/journal/aerospace

Aerospace 2024,11, 920 2 of 17
conversion, power storage, and power distribution functions for the other subsystems of
the satellite [
13
,
14
]. The mechanical and electrical design of the EPS requires an in-depth
understanding of the mission requirements and consideration of issues such as electro-
magnetic interference, energy balance over life, electrostatic discharge immunity, corona,
single-component failures, redundancy, autonomous operation, thermal design margins,
and fault recovery [
15
]. Different from other applications involving storage systems (such
as microgrids [
16
–
19
], charging stations [
20
–
22
], and residential systems [
23
,
24
]), solar
panels are not at maximum because of the spacecraft’s relative position (eclipse phase) over
time with the sun and Earth. Therefore, one of the key elements involved in increasing the
lifespans of the batteries is controlling and monitoring the battery charge cycling curve, as
detailed in [
25
]. In a low Earth orbit (LEO) application, battery charging must be completed
in one hour, and during its life, it will usually experience 30,000 to 50,000 cycles. The
overcharging of batteries must not take place, and the depth of their overcharge must be
under the threshold for the extension of the battery’s life. The solar array output charac-
teristics must be matched to the satellite bus and the batteries [
26
]. The spacecraft turns
on its transmission and payload at specific locations above the Earth depending on the
satellite constellation. In other words, the spacecraft’s subsystems do not require constant
power at all stages during its mission life, so a direct energy transmission system is not
suitable in this case. Therefore, an efficient PCU is needed to control and monitor the power
management of the EPS. The main focus of this paper is to design a converter that can
extract power from two solar panels at a time. In the literature on two-input converter
designs, one input is taken as a solar panel while another input is taken from the batter-
ies [
27
]. Refs. [
28
,
29
] discussed PCUs for space applications; however, the redundancy
features with the associated size were neglected. So, the second focus of this paper is to
extract maximum power from the solar panels with added redundancy features. For this
purpose, an MPPT-based interleaved boost converter is designed. Many MPPT techniques
are available in the literature, i.e., constant voltage (CV), perturbation and observation (PO),
the incremental conductance (IC) method, etc. [
30
]. In this paper, a CV MPPT technique is
used, which is very simple and reasonably efficient compared to other techniques [
31
]. As
single-phase topology used to be the norm for small satellite power management systems,
inspired by multistage interleaved topology, this paper endeavors to explore this approach
in small satellite applications to achieve efficient design along with reduced ripples.
2. Converter Design
The PCU is mounted with the Attitude Determination and Control Subsystem (ADCS)
onto a single PCB of the satellite. The new modular approach makes use of a standardized
module, as can be seen in Figure 1. Photographs of 1U CubeSat submodules and the ISIS-1
Unit CubeSat structure are shown in Figure 1. The cross-sectional view of the CubeSat
module shows that the solar panels are mounted at the top of the PCB, the reconfigurable
magnetorquer traces are embedded inside the PCB internal layers and the power manage-
ment subsystem and its coil driver are mounted at the bottom of the PCB [
32
,
33
]. This design
optimization significantly reduces the satellite’s footprint, consequently decreasing both
its weight and overall cost. The previous power management architecture based on single-
phase topology is detailed in reference [
34
], while the integrated ADCS is comprehensively
described in reference [35].

Aerospace 2024,11, 920 3 of 17
Aerospace 2024, 11, 920 3 of 18
Figure 1. PCB layout and components placement.
When one panel is at a right angle to solar radiation, it receives maximum sunlight,
and the output voltage of the panel is 6.6 V. When two panels are positioned at 45° to the
sunlight, some of the cells are unable to receive adequate solar radiation, resulting in a
reduction in output voltage. In the case of three panels, the output voltage decreases
further. It is assumed that the panel output voltage varies from 2 V to 6.6 V. This variable
output from the solar panels is fed into a converter to transform it to the PDB level.
Figure 1. PCB layout and components placement.
When one panel is at a right angle to solar radiation, it receives maximum sunlight,
and the output voltage of the panel is 6.6 V. When two panels are positioned at 45
◦
to the
sunlight, some of the cells are unable to receive adequate solar radiation, resulting in a
reduction in output voltage. In the case of three panels, the output voltage decreases further.
It is assumed that the panel output voltage varies from 2 V to 6.6 V. This variable output
from the solar panels is fed into a converter to transform it to the PDB level. Normally,

Aerospace 2024,11, 920 4 of 17
the input dynamic range of the converter is very low, making it impossible for a single
converter to cover this wide input range to the PDB level.
The block diagram of the MPPT-based interleaved converter system is shown in
Figure 2. The converter consists of two parallel blocks, labeled converter-1 and converter-2.
Converter-1 has an input range from 2.2 V to 4.4 V, while converter-2 has an input range
of 4.4 V to 6.6 V. A block diagram of the designed EPS is presented in Figure 3a. The
conventional schematic design from [
34
], with added redundancy for the PCM module,
is illustrated in Figure 3b. The schematic of the proposed MPPT-based interleaved boost
converter, featuring similar redundancy and the same output characteristics but with fewer
electronic components, is designed to convert the variable output of the solar panels (2.2 V
to 6.6 V) to the PDB voltage level (14 ±2 V), as shown in Figure 3c.
Aerospace 2024, 11, 920 4 of 18
Normally, the input dynamic range of the converter is very low, making it impossible for
a single converter to cover this wide input range to the PDB level.
The block diagram of the MPPT-based interleaved converter system is shown in
Figure 2. The converter consists of two parallel blocks, labeled converter-1 and convert-
er-2. Converter-1 has an input range from 2.2 V to 4.4 V, while converter-2 has an input
range of 4.4 V to 6.6 V. A block diagram of the designed EPS is presented in Figure 3a.
The conventional schematic design from [34], with added redundancy for the PCM
module, is illustrated in Figure 3b. The schematic of the proposed MPPT-based inter-
leaved boost converter, featuring similar redundancy and the same output characteristics
but with fewer electronic components, is designed to convert the variable output of the
solar panels (2.2 V to 6.6 V) to the PDB voltage level (14 ± 2 V), as shown in Figure 3c.
Figure 2. Schematic of the MPPT interleaved boost converter.
(a)
Figure 2. Schematic of the MPPT interleaved boost converter.
Aerospace 2024, 11, 920 4 of 18
Normally, the input dynamic range of the converter is very low, making it impossible for
a single converter to cover this wide input range to the PDB level.
The block diagram of the MPPT-based interleaved converter system is shown in
Figure 2. The converter consists of two parallel blocks, labeled converter-1 and convert-
er-2. Converter-1 has an input range from 2.2 V to 4.4 V, while converter-2 has an input
range of 4.4 V to 6.6 V. A block diagram of the designed EPS is presented in Figure 3a.
The conventional schematic design from [34], with added redundancy for the PCM
module, is illustrated in Figure 3b. The schematic of the proposed MPPT-based inter-
leaved boost converter, featuring similar redundancy and the same output characteristics
but with fewer electronic components, is designed to convert the variable output of the
solar panels (2.2 V to 6.6 V) to the PDB voltage level (14 ± 2 V), as shown in Figure 3c.
Figure 2. Schematic of the MPPT interleaved boost converter.
(a)
Figure 3. Cont.

Aerospace 2024,11, 920 5 of 17
Aerospace 2024, 11, 920 5 of 18
(b)
(c)
Figure 3. (a) Block level representation of ADS and ACS intercommunication with the onboard
computer system OBC. (b) Conventional PCM schematic design. (c) Proposed schematic design
with interleaved converter.
2.1. Schematic Design Description
The PCM supervises baery charging, voltage regulation, and overall health moni-
toring of various subsystems. It regulates the unstable voltage (2 V to 6 V) to a stable
VSS
75 VSS
65 VSS
45 VSS
36 VSS
15 AVSS
31
C3IN1+/VCMPST3/RP71/RD7 84
C3IN2-/RP70/RD6 83
C2IN1-/PMA2/RPI121/RG9 14
C2IN3-/SDO2/PMA3/RP120/RG8
12 C1IN1-/SDI2/PMA4/RPI119/RG7
11
C1IN3-/SCK2/PMA5/RP118/RG6 10
PGEC2/SOSCO/C3IN1-/T1CK/RPI62/RC14 74
PGED2/SOSCI/C3IN3-/RPI61/RC13 73
PGED1/AN7/RCV/RPI39/RB7 27
PGEC1/AN6/RPI38/RB6 26
PGEC3/AN1/RPI33/RB1 24
PGED3/AN0/RPI32/RB0 25
AN31/PMD7/RP87/RE7
5
AN30/PMD6/RPI86/RE6
4AN29/PMD5/RP85/RE5
3AN28/PMD4/RP84/RE4
100
AN27/PMD3/RPI83/RE3
99
AN26/PMD2/RP82/RE2
98
AN25/PMD1/RPI81/RE1
94
AN24/PMD0/RP80/RE0
93
AN23/RPI23/RA7
92 AN22/RPI22/RA6
91 AN21/RPI89/RE9
19 AN20/RPI88/RE8
18
AN19/RPI52/RC4
9
AN18/RPI51/RC3 8
AN17/RPI50/RC2 7
AN16/RPI49/RC1 6
AN15/PMA0/RPI47/RB15 44
AN14/PMA1/RPI46/RB14 43
AN13/PMA10/RPI45/RB13
42 AN12/PMA11/RPI44/RB12
41
AN11/PMA12/RPI43/RB11
35 AN10/CVREF/PMA13/RPI42/RB10
34
AN9/PMA7//RPI41/RB9 33
AN8/PMA6/RPI40/RB8 32
AN5/C1IN1+/VBUSON/VBUSST/RPI37/RB5
20
AN4/C1IN2-/USBOEN/RPI36/RB4
21
AN3/C2IN1+/VPIO/RPI35/RB3 22
AN2/C2IN2-/VMIO/RPI34/RB2
23
VUSB3V3
55
VCAP
85 AVDD
30 VDD
86 VDD
62 VDD
46 VDD
37 VDD
16 VDD
2
RPI124/RG12
96
RPI78/RD14 47
RPI77/RD13 80
RPI76/RD12 79
RPI31/RA15 67
RPI30/RA14 66
RP127/RG15 1
RP126/RG14 95
RP125/RG13 97
RP113/RG1 89
RP112/RG0 90
RP109/RF13 39
RP108/RF12 40
RP104/RF8 53
RP98/RF2 52
RP79/RD15 48
SDA2/PMA9/RP100/RF4 49
SCL2/PMA8/RP101/RF5 50
ASDA2/RPI19/RA3 59
ASCL2/RPI18/RA2 58
ASCL1/PMCS2/RPI74/RD10 70
ASDA1/DPLN/RPI73 /RD9 69
RTCC/DMLN/RPI72/RD8 68
PMCS1/RPI75/RD11 71
PMRD/RP69/RD5 82
PMWR/RP68/RD4 81
PMBE/RP67/RD3 78
INT0/DMH/RP64/RD0 72
VCPCON/RP65/RD1
76
DPH/RP66/RD2 77
USBID/RP99/RF3
51
VCMPST2/RP97/RF1 88
VCMPST1/RP96/RF0 87
D-/RG3
56 D+/RG2
57
OSC2/CLKO/RC15 64
OSC1/RPI60/RC12 63
VREF+/RA10
29 VREF-/RA9
28
TDO/RPI21/RA5 61
TDI/RPI20/RA4
60
TCK/RPI17/RA1
38
TMS/RPI16/RA0 17
MCLR
13
VBUS
54
U*
PIC24HJ256GP610-N
INH 1
RTH 8
RTL 9
WAKE 7
CANH 11
CANL 12
VCC 10
BAT 14
EN
6STB
5ERR
4TXD
2RXD
3GND
13 *
TJA1055-n1
INH 1
RTH 8
RTL 9
WAKE 7
CANH 11
CANL 12
VCC 10
BAT 14
EN
6STB
5ERR
4TXD
2RXD
3GND
13
*
TJA1055-N2
Y? GND
EN
14
NC
15
GND
16
II
Q18
NC NC
NC 20
NC 21
*
TLS715B0E
1
1
4
4
3
3
2
2
*
Header 4
100pF
100pF
1
1
6
6
5
5
4
4
8
8
7
7
3
3
2
2
9
9
D9-1
100pF
700k
700k
700k
700k
20k
700k
500k
700k
Q?
VCC
Q?
D4
100pF
3.3
500k
10k
500k
VOUT 8
SNS 7
CPSRR
2GND
5NC
3VIN
1
*
MIC5282YMME
500k
WDI 1
GND
2
NC
3SET0 4
SET1 5
SET2 6
*WDO 7
VCC 8
*
MAX6373KA+T
500k
500k
100k
100pF
11
66
55
44
88
77
33
22
99
10 10
11 11
12 12
13 13
14 14
15 15
*
D15-SPU
3.3
100nF
VCC
TCK
TCK
100pF
700k
VCC
+5
TEST/SBWTCK
1
DVCC
2
P2.5/R OSC/CA5
3
DVCC
4
XOUT/P2.7/CA7 5
XIN/P2.6/CA6 6
*RST/NMI/SBWTDIO
7
P2.0/ACLK/A0/CA2
8
P2.1/TAINCLK/SMCLK/A1/CA3
9
P2.2/TA0.0/A2/CA4/CAOUT 10
P3.0/UCB0STE/UCA0CLK/A5
11
P3.1/UCB0SIMO/UCB0SDA
12
P3.2/UCB0SOMI/UCB0SCL 13
P3.3/UCB0CLK/UCA0STE
14
P3.4/UCA0TXD/UCA0SIMO 15
P3.5/UCA0RXD/UCA0SOMI 16
P3.6/TA1.0/A6 17
P3.7/TA1.1/A7 18
P2.3/TA0.1/A3/VREF/VEREF/CA0 19
P2.4/TA0.2/A4/VREF+/VEREF+/CA1
20
P1.0/TACLK/ADC10CLK/CAOUT 21
P1.1/TA0.0/TA1.0
22
P1.2/TA0.1
23
P1.3/TA0.2
24
P1.4/SMCLK/TCK 25
P1.5/TA0.0/TMS 26
P1.6/TA0.1/TDI/TCLK 27
P1.7/TA0.2/TDO/TDI
28
msp430
1
OUT
GND 2
VIN- 4
V+ 5
VIN+ 3
*
INA168NA/250
30pf
30pf
1
1
4
4
3
3
2
2
HEADER-4-msp
100pF
100pF
175k
+5
100pF
3.3
200k
10k
10k
100k
+5
VOUT 8
SNS 7
CPSRR
2GND
5NC
3VIN
1
MIC5282YMME
WDI 1
GND
2
NC
3SET0 4
SET1 5
SET2 6
*WDO 7
VCC 8
MAX6373KA+T
10uF
0.007
10uF
3.3
4uF
Vo
1
GND
2
VIN- 4
VCC
5
VIN+ 3
*
INA168-PDU
700k
200k
100k
100pF
100pF
175k
VOUT 6
GND 4
VIN-
1
VCC
8
VIN+
2
Vref 3
ROS 5
*
ina170-PDU
1
1
6
6
5
5
4
4
8
8
7
7
3
3
2
2
9
9
D9 battery
700k
200k
100k
10nf10M
TEST/SBWTCK
1
DVCC
2
P2.5/R OSC/CA5
3
DVCC
4
XOUT/P2.7/CA7 5
XIN/P2.6/CA6 6
*RST/NMI/SBWTDIO
7
P2.0/ACLK/A0/CA2
8
P2.1/TAINCLK/SMCLK/A1/CA3
9
P2.2/TA0.0/A2/CA4/CAOUT 10
P3.0/UCB0STE/UCA0CLK/A5
11
P3.1/UCB0SIMO/UCB0SDA
12
P3.2/UCB0SOMI/UCB0SCL 13
P3.3/UCB0CLK/UCA0STE
14
P3.4/UCA0TXD/UCA0SIMO 15
P3.5/UCA0RXD/UCA0SOMI 16
P3.6/TA1.0/A6 17
P3.7/TA1.1/A7 18
P2.3/TA0.1/A3/VREF/VEREF/CA0 19
P2.4/TA0.2/A4/VREF+/VEREF+/CA1
20
P1.0/TACLK/ADC10CLK/CAOUT 21
P1.1/TA0.0/TA1.0
22
P1.2/TA0.1
23
P1.3/TA0.2
24
P1.4/SMCLK/TCK 25
P1.5/TA0.0/TMS 26
P1.6/TA0.1/TDI/TCLK 27
P1.7/TA0.2/TDO/TDI
28
msp430
1
OUT
GND 2
VIN- 4
V+ 5
VIN+ 3
*
INA168NA/250
30pf
30pf
1
1
4
4
3
3
2
2
HEADER-4-msp
100pF
100pF
175k
100pF
3.3
200k
10k
10k
100k
+5
VOUT 8
SNS 7
CPSRR
2GND
5NC
3VIN
1
MIC5282YMME
WDI 1
GND
2
NC
3SET0 4
SET1 5
SET2 6
*WDO 7
VCC 8
MAX6373KA+T
10uF
0.007
3.3
4uF
TEST/SBWTCK
1
DVCC
2
P2.5/R OSC/CA5
3
DVCC
4
XOUT/P2.7/CA7 5
XIN/P2.6/CA6 6
*RST/NMI/SBWTDIO
7
P2.0/ACLK/A0/CA2
8
P2.1/TAINCLK/SMCLK/A1/CA3
9
P2.2/TA0.0/A2/CA4/CAOUT 10
P3.0/UCB0STE/UCA0CLK/A5
11
P3.1/UCB0SIMO/UCB0SDA
12
P3.2/UCB0SOMI/UCB0SCL 13
P3.3/UCB0CLK/UCA0STE
14
P3.4/UCA0TXD/UCA0SIMO 15
P3.5/UCA0RXD/UCA0SOMI 16
P3.6/TA1.0/A6 17
P3.7/TA1.1/A7 18
P2.3/TA0.1/A3/VREF/VEREF/CA0 19
P2.4/TA0.2/A4/VREF+/VEREF+/CA1
20
P1.0/TACLK/ADC10CLK/CAOUT 21
P1.1/TA0.0/TA1.0
22
P1.2/TA0.1
23
P1.3/TA0.2
24
P1.4/SMCLK/TCK 25
P1.5/TA0.0/TMS 26
P1.6/TA0.1/TDI/TCLK 27
P1.7/TA0.2/TDO/TDI
28
msp430
1
OUT
GND 2
VIN- 4
V+ 5
VIN+ 3
*
INA168NA/250
30pf
30pf
1
1
4
4
3
3
2
2
HEADER-4-msp
100pF
100pF
175k
100pF
3.3
200k
10k
10k
100k
+5
VOUT 8
SNS 7
CPSRR
2GND
5NC
3VIN
1
MIC5282YMME
WDI 1
GND
2
NC
3SET0 4
SET1 5
SET2 6
*WDO 7
VCC 8
MAX6373KA+T
10uF
0.007
3.3
4uF
TEST/SBWTCK
1
DVCC
2
P2.5/R OSC/CA5
3
DVCC
4
XOUT/P2.7/CA7 5
XIN/P2.6/CA6 6
*RST/NMI/SBWTDIO
7
P2.0/ACLK/A0/CA2
8
P2.1/TAINCLK/SMCLK/A1/CA3
9
P2.2/TA0.0/A2/CA4/CAOUT 10
P3.0/UCB0STE/UCA0CLK/A5
11
P3.1/UCB0SIMO/UCB0SDA
12
P3.2/UCB0SOMI/UCB0SCL 13
P3.3/UCB0CLK/UCA0STE
14
P3.4/UCA0TXD/UCA0SIMO 15
P3.5/UCA0RXD/UCA0SOMI 16
P3.6/TA1.0/A6 17
P3.7/TA1.1/A7 18
P2.3/TA0.1/A3/VREF/VEREF/CA0 19
P2.4/TA0.2/A4/VREF+/VEREF+/CA1
20
P1.0/TACLK/ADC10CLK/CAOUT 21
P1.1/TA0.0/TA1.0
22
P1.2/TA0.1
23
P1.3/TA0.2
24
P1.4/SMCLK/TCK 25
P1.5/TA0.0/TMS 26
P1.6/TA0.1/TDI/TCLK 27
P1.7/TA0.2/TDO/TDI
28
msp430
1
OUT
GND 2
VIN- 4
V+ 5
VIN+ 3
*
INA168NA/250
30pf
30pf
1
1
4
4
3
3
2
2
HEADER-4-msp
100pF
100pF
175k
100pF
3.3
200k
10k
10k
100k
+5
VOUT 8
SNS 7
CPSRR
2GND
5NC
3VIN
1
MIC5282YMME
WDI 1
GND
2
NC
3SET0 4
SET1 5
SET2 6
*WDO 7
VCC 8
MAX6373KA+T
10uF
0.007
3.3
4uF
1
16
6
5
5
4
4
8
87
7
3
3
2
2
9
9
D9 PDU
10k
100uH
100uH
1.0uF 100k
1.0uF
100uH
100uH
1.0uF
1.0uF
1.0uF 100k
1.0uF
100uH
100uH
1.0uF
1.0uF
1.0uF 100k
1.0uF
100uH
100uH
1.0uF
1.0uF
1.0uF 100k
1.0uF
PCM main
controller
Solar Panel
Input
Watch-dog
timer
Voltage sensor
Latch-up
protection
Low dropout
voltage regulator
MPPT based interleaved boost converter-1 MPPT based interleaved boost converter-2
MPPT based interleaved boost converter-3 MPPT based interleaved boost converter-4
CAN Transciever
JTAG
Crystal Oscillator
Output to
Output to
Bidirectional current sensor
voltage sensor
batteries
PDU
PIC24
Figure 3. (a) Block level representation of ADS and ACS intercommunication with the onboard
computer system OBC. (b) Conventional PCM schematic design. (c) Proposed schematic design with
interleaved converter.

Aerospace 2024,11, 920 6 of 17
2.1. Schematic Design Description
The PCM supervises battery charging, voltage regulation, and overall health monitor-
ing of various subsystems. It regulates the unstable voltage (2 V to 6 V) to a stable voltage
level suitable for the power distribution bus (PDB) (14 ±2 V). To drive the solar panels at
their maximum power point (MPP), an efficient interleaved boost converter is designed
and simulated. The MPPT boost converter can be implemented using various techniques,
as described in [
30
]. Based on considerations of efficiency and computational simplicity,
the constant voltage method is selected for the design of the PCM [
31
]. The solar power
density at low Earth orbit (LEO) is approximately 1366 W/m
2
, and the average day for
a satellite is about 60% of the total revolution time (with a 40% eclipse period). During
its rotation around the Earth, one, two, or at most three panels (when one corner of the
satellite faces the sunlight) are exposed to solar radiation.
The conventional redundant design of the PCM consists of four redundant and mod-
ular MPPT submodules. Each boost converter is connected to a local microprocessor
(MSP430) that has various housekeeping sensors. While this design is effective for single-
component failures, it increases the cost, size, and mass of the power management tiles.
To address the solar panel input variations while reducing costs, mass, and size, a single
MPPT-based interleaved converter is designed.
The battery charging system is controlled through redundant power bus lines in-
terfaced with the PDB via a DB-9 connector [
36
,
37
]. The central PCM ‘PIC24’ controller
communicates with the onboard computer (OBC) subsystem for power management
and operations of the entire module. ‘PIC24’ communicates with the OBC using a dual-
redundant Controller Area Network (CAN). The casing dimensions of the PCM include
standardized connector interfaces (input/output power/signal), making the system com-
pletely modular and adaptable to Plug-and-Play (PnP) features, requiring minimal user
intervention.
Low-cost passive voltage and temperature sensors are utilized to manage power
consumption and maintain the thermal envelope within design requirements. A high-side
bidirectional current sensor is installed at the battery input to monitor the battery charge
cycling curve. Additionally, current and voltage sensors are employed at the output of the
solar power unit (input to the proposed interleaved converter).
The MPPT controller (PIC24) communicates with the OBC via SPI protocol through its
own transceiver and redundant CAN buses. The PCM monitors the health of the batteries,
solar panels, and power distribution module, providing sufficient telemetry to the OBC
through the CAN interface.
For power interfacing, the PCM receives two redundant power inputs from four
independent solar panels through two D-type connectors. The PCM power distribution
bus supplies an unregulated voltage level of 14
±
2 V, which the PDM converts into various
regulated voltage levels. To monitor power flow, each redundant input line from the PCM
is equipped with a current sensor, while a single voltage sensor tracks the PDB’s voltage
level. These sensors ensure proper monitoring of the current drawn by the PDM and the
voltage supplied by the PDB. To ensure modularity, all input connectors are male and all
output connectors are female.
Solar radiation makes CMOS-based COTS components prone to latch-ups. A latch-up
is a transient effect that allows high current to flow through the device from the power
supply to ground, short-circuiting the circuitry and potentially damaging the system. This
issue can be mitigated by incorporating bipolar devices into the circuitry, as they offer
immunity to latch-ups because a significant amount of energy is required to trigger such
events. However, the microprocessors remain CMOS-based and still require latch-up
protection circuits. To address this issue, a latch-up protection system is designed and
simulated according to [
34
], reducing the likelihood of radiation-induced latch-ups in the
PCM module. The same latch-up protection circuits used for the PIC MCU in the PDU/PCU
are also implemented across other subsystems within the satellite. These circuits provide

Aerospace 2024,11, 920 7 of 17
consistent protection against momentary latch-ups caused by solar radiation, ensuring
safeguarding for the entire system, not just the MCU [34].
The EPS features four solar panels that cover multiple faces of the satellite. Each panel
measures 16
×
16 cm
2
, utilizing triple-junction GaAs CESI solar cells. The solar cells have
an efficiency of 29%, generating 2.2 V with a current of 0.46 A, resulting in an output power
of 1.012 W per cell. Each solar cell measures 70
×
40 mm
2
and occupies an area of 2800 mm
2
.
Given these dimensions, six solar cells are mounted on each panel, arranged in two strings
of three cells in series, each with bypass diodes. A protection diode is connected at the
end of the panel. The bypass diodes ensure the solar panel continues to operate effectively
in the event of a single cell failure, while the protection diode safeguards the cells from
reverse current flow from other satellite subsystems.
The solar panel outputs a voltage of 6.6 V with an output current of 0.96 A. Current
and voltage sensors are mounted on the output power bus (voltage level of 6.6 V and
current of 0.96 A) of the solar panel. Additionally, single current and voltage sensors are
installed on the power distribution bus (PDB), which operates at a voltage level of 14
±
2 V.
An overvoltage protection circuit safeguards the PDB from excessive voltage conditions.
Energy is stored in a single pack of NiCd rechargeable batteries [
38
]. This pack consists
of ten NiCd cells, each providing 1.2 V for a total of 12 V. The capacity of each NiCd cell is
0.9 Ah, resulting in a maximum available energy of 10.8 Wh, equivalent to 38.9 kJ. All these
batteries are charged from the PDB, which, in turn, is powered by the four solar panels
through a hysteretic switching boost converter. With an efficiency of 93%, the expected
average power available at the PDB for recharging the batteries is 5.65 W. Consequently,
the expected recharge time for a single cell is 1.91 h, while the recharge time for the entire
system is 19.1 h. The worst-case efficiency (discharge energy/charge energy) of the battery,
across the temperature range and radiation environment, is 80%, resulting in an average
power of 8.64 W available for all electronic systems.
2.2. MPPT Based on Constant Voltage Technique
The MPPT is implemented in the interleaved boost converter using the hysteresis
loop of the comparator. Typically, comparators have an internal hysteresis of 5 mV to
10 mV, which protects them from unwanted oscillations due to noise signals. To mitigate
oscillations from noise signals above 10 mV, an external hysteresis of about 600 mV is added
to the comparator.
The input switching voltage from the solar panel is variable. This incoming voltage
is scaled by a resistive divider network and sent to the non-inverting input of the com-
parator. When this input voltage reaches 6.6 V, which is greater than the reference voltage
(
Vre f =6V
), the output of the comparator goes high and turns on the transistor. As a result,
the voltage across the input filter capacitor
C1
decreases, leading to a reduction in the input
voltage to the comparator. However, the output remains high until the input voltage drops
below 6 V. Once the input falls below 6 V, the output of the comparator goes low, turning
off the switching transistor. The difference between the two voltage limits—low (6 V) and
high (6.6 V)—is referred to as the hysteresis window.
To calculate the values of the resistive network
R1
,
R2
, and
R3
, the hysteresis window
band
VHB
(with
VL=6V
and
VH
= 6.6 V) is chosen, resulting in a range of 600 mV, and
VCC = 10 V. For this calculation, we select a value for R3(in this case, R3=1MΩ).
R1=R3VHB
VCC (1)
From (1), the R1resistor value is R1= 20 kΩ.
The Vre f value is found using (4)
VH>Vre f 1+VHB
VCC (2)

Aerospace 2024,11, 920 8 of 17
which results in Vref < 6.65 V, and the Vref value of 6.6 V is chosen.
To find R2, we rewrite the equation as
R2=1
h VH
Vre f ×R1−1
R1−1
R3i (3)
This results in
R2
= 1123 k
Ω
. Using the same methodology, values for the converter-1
hysteresis comparator block are found.
2.3. Mathematical Model
The analysis of a two-level interleaved boost converter using the state space averaging
technique involves examining the converter’s performance with a duty cycle ranging from
0.5 to 1. This assessment considers the impact of parasitic elements and explores the circuit’s
behavior across four distinct operational modes.
In Mode-1, when switch S1 is closed and S2 is open, the inductor currents
IL1
and
IL2
exhibit specific behaviors as IL1rises and IL2falls.
By analyzing Figure 2and applying Kirchhoff’s Voltage Law (KVL) and Kirchhoff’s
Current Law (KCL), equations are derived and represented in matrix form for comprehen-
sive analysis. Figure 4depicts the modes of operation.
Aerospace 2024, 11, 920 8 of 18
𝑅=1
 𝑉
𝑉×𝑅−󰇡1
𝑅󰇢−󰇡1
𝑅󰇢 (3)
This results in 𝑅 = 1123 kΩ. Using the same methodology, values for the convert-
er-1 hysteresis comparator block are found.
2.3. Mathematical Model
The analysis of a two-level interleaved boost converter using the state space aver-
aging technique involves examining the converter’s performance with a duty cycle
ranging from 0.5 to 1. This assessment considers the impact of parasitic elements and
explores the circuit’s behavior across four distinct operational modes.
In Mode-1, when switch S1 is closed and S2 is open, the inductor currents 𝐼 and
𝐼 exhibit specific behaviors as 𝐼 rises and 𝐼 falls.
By analyzing Figure 2 and applying Kirchhoff’s Voltage Law (KVL) and Kirchhoff’s
Current Law (KCL), equations are derived and represented in matrix form for compre-
hensive analysis. Figure 4 depicts the modes of operation.
Figure 4. Modes of operation of the two inputs interleaved converter.
The state variables are 𝑖
𝑖
𝑉
A1=⎣
⎢
⎢
⎡
−(𝑟+𝑟)/𝐿1 0 0
0−
(𝑟+𝑟)+𝑅𝑟
𝑅+𝑟
/𝐿2 −𝑅/(𝑅+𝑟
)𝐿2
0𝑅/𝐶
(𝑅+𝑟
)−1/𝐶(𝑅+𝑟
)⎦
⎥
⎥
⎤
𝐵1=⎣
⎢
⎢
⎢
⎡
1
𝐿00
1
𝐿0−
1
𝐿
00 0
⎦
⎥
⎥
⎥
⎤
Figure 4. Modes of operation of the two inputs interleaved converter.
The state variables are 

iL1
iL2
VC


A1 =


−(rL1+rs1)/L1 0 0
0−h(rL2+rd2)+Rrc
R+rci/L2−R/(R+rc)L2
0R/C(R+rc)−1/C(R+rc)



B1=


1
L10 0
1
L20−1
L2
0 0 0




Aerospace 2024,11, 920 9 of 17
C1 =h0Rrc
(R+rc)R
(R+rc)i
In Mode-2, both switches S1 and S2 are closed, resulting in a scenario where the
inductor currents IL1and IL2are simultaneously increasing.
A2 =


−1
L1(rL1+rs1)0 0
0−(rL2+rS2)
L20
0 0 −1
c(R+rc)



B2=


1
L10 0
1
L20 0
0 0 0



C2 =h0 0 R
(R+rc)i
In Mode-3, switch S1 is open while S2 is closed, leading to a situation where the
inductor current IL1is decreasing, and IL2is increasing.
A3=



−1
L1(RrC+(R+rC)(rL1+rd1))
(R+rC)0−R
L1(R+rC)
0−(rL2+rS2)
L20
R
C(R+rC)0−1
C(R+rC)




B3=


1
L1
−1
L10
1
L20 0
0 0 0



C3=hRrc
(R+rc)0R
(R+rc)i
In Mode-4, both switches S1 and S2 are closed, causing the inductor currents
IL1
and
IL2to increase
A4 =


−1
L1(rL1+rS1)0 0
0−(rL2+rS2)
L20
0 0 −1
C(R+rC)



B4=


1
L10 0
1
L20 0
0 0 0



C4=h0 0 R
(R+rC)i
Based on the premise that all switching cells carry an equal average current and
are operated at the same duty ratio within a specific switching cycle, we can derive the
following information:
d2i=1
N−d(4)
i=1, 2 . . . . . . N
d—Duty ratio
When the duty cycle dremains constant from one cycle to the next, it is referred to as
the steady-state duty ratio D. The averaged state space model over a specific cycle can be
expressed as .
x=Ax +BVS(5)
Applying (3) to the waveforms illustrated in Figure 2, we derive the following results:
A=∑2N
j=1djAj(6)

Aerospace 2024,11, 920 10 of 17
B=∑2N
j=1djBj(7)
C=∑2N
j=1djCj(8)
where Aj and bj represent the state matrix and control vector for the duration of interval
djTs, respectively.
And j=1, 2, . . . , 2 N.
Now, assuming that d=D, we can utilize (4) and (6) to express
A=D∑N
i=1A2i−1+1
N−D∑N
i=1A2i(9)
Likewise, we can express (7) in a similar manner.
B=D∑N
i=1B2i−1+1
N−D∑N
i=1B2i(10)
Similarly, we can write (8) similar manner.
C=D∑N
i=1C2i−1+1
N−D∑N
i=1C2i(11)
Substitute N=2 in the above equations
A=(A1+A3)(1−D) + (2D−1)A2
B=(B1+B3)(1−D) + (2D−1)B2
C=(C1+C3)(1−D) + (2D−1)C2
In the analysis of small-signal behavior, we assume that the duty cycle ddd varies
from cycle to cycle. Equations (9)–(11), along with the perturbations in the input voltage,
duty ratio, and states, are incorporated into Equation (5). By neglecting the non-linear
second-order term, we derive the perturbed state-space equation for an N-phase interleaved
converter.
e
x=AX +BVS+Ae
x+B
∼
VS+∑N
i=1A2i−1−
A2iX+∑N
i=1(B2i−1−B2i)VSie
d
When all perturbations are assumed to be zero, we derive the steady-state model as
follows:
X=−A−1BVS
Therefore, the small-signal model can be expressed as follows:
e
x=Ae
x+B
∼
VS+h∑N
i=1(A2i−1−A2i)X+∑N
i=1(B2i−1−B2i)VS]e
d
e
x=Ae
x+B
∼
VS+[(A1+A3−2A2)X+(B1+B3−2B2)VS]
∼
d
Apply the Laplace Transform
se
x(s) = Ae
x(s) + B
∼
VS(s) + [(A1+A3−2A2)X+(B1+B3−2B2)VS]e
d(s)
e
x(s) = [sI −A]−1B
∼
VS(s) + [(A1+A3−2A2)X+(B1+B3−2B2)VS]]
∼
d(s)
K=[(A1+A3−2A2)]
T=[(B1+B3−2B2)]

Aerospace 2024,11, 920 11 of 17
e
x(s) = [sI −A]−1B
∼
VS(s) + [(K)X+ (T)VS]e
d(s)
∼
vO(s) = CT∼
x(s)
∼
vO(s) = CT[sI −A]−1B
∼
VS(s) + [(K)X+ (T)VS]∼
d(s)
∼
vO(s) = CTe
x(s)
VO=[(C1+C3)(1−d) + (2d−1)C2]X
vO=VO+∼
vO,x=X+e
x,d=D+e
d
vO=VO+∼
vO=h(C1+C3)(1−(D+e
d) + (2(D+e
d)−1C2](X+e
x)
vO=VO+∼
vO=(C1+C3)(1−D−
∼
d) + 2D+2e
d−1DC2](X+e
x)
After the simplification of the above equation, we obtain the following:
∼
v0=[(C1+C3)(1−D)+(2D−1)C2]e
x+[(2C2−C1−C3)X]e
d
P=[(C1+C3)(1−D)+(2D−1)C2]
Q=(2C2−C1−C3)
∼
vO(s)= [P]
∼
x(s) + [QX]e
d(s)
e
x(s) = [sI −A]−1B
∼
VS(s) + [(K)X+ (T)VS]e
d(s)
Substitute e
x(s)in the voltage equation
∼
vO(s) = P[sI −A]−1[B¯
VS(s) + [(K)X+ (T)VS]]
∼
d(s) + [QX]e
d(s)
Substitute B
∼
VS(s) = 0
∼
vO(s) = P[sI −A]−1[(K)X+ (T)VS]
∼
d(s) + [QX]e
d(s)
In conclusion, the transfer function from the output to variations in the duty ratio can
be represented as
vO(s)
¯
d(s)=P[sI −A]−1[(K)X+(T)VS]+[QX](12)
2.4. Stability Analysis of the Converter Without a Compensator
The transfer function of converter-2 is given in (13), utilizing the feedback loop of
converter-1 and -2
GT(s) = Gc(s)Gvd (s)H(s)(13)
where G
T
(s) is the loop transfer function, G
vd
(s) is the control-to-output transfer function,
G
c
(s) is the MPPT block transfer function, and H(s) is the attenuation network transfer
function. In the case of converter-2, H(s) is a voltage divider network with an attenuation
factor of 0.8, while Gc(s) has a value of 0.25. In order to find Gvd(s) for converter-2, a small
signal model is drawn, as shown in Figure 5. This model is converted to a transformer
model and all the elements are shifted to the load side. The resultant transfer function of
the Gvd(s) is given in (14)
Gvd(s) = V
D’
1+sL I
V
1+L
RD’2s+s2LC
D’2
(14)

Aerospace 2024,11, 920 12 of 17
Aerospace 2024, 11, 920 12 of 18
The transfer function of converter-2 is given in (13), utilizing the feedback loop of
converter-1 and -2 𝐺(𝑠)=𝐺(𝑠)𝐺(𝑠)𝐻(𝑠) (13)
where G
T
(s) is the loop transfer function, G
vd
(s) is the control-to-output transfer function,
G
c
(s) is the MPPT block transfer function, and H(s) is the aenuation network transfer
function. In the case of converter-2, H(s) is a voltage divider network with an aenuation
factor of 0.8, while G
c
(s) has a value of 0.25. In order to find G
vd
(s) for converter-2, a small
signal model is drawn, as shown in Figure 5. This model is converted to a transformer
model and all the elements are shifted to the load side. The resultant transfer function of
the G
vd
(s) is given in (14)
𝐺(𝑠)= 𝑉
𝐷󰆒1+𝑠𝐿𝐼
𝑉
1+ 𝐿
𝑅𝐷󰆒𝑠+𝑠𝐿𝐶
𝐷󰆒 (14)
Puing parameters values in (14) and inserting (14) into (13) results in G
T
(s), as given
in (15)
𝐺(𝑠)=27 1+23×10𝑠
1+25×10𝑠+123×10𝑠 (15)
Inserting the values of G
c
(s), H(s) and G
vd
(s) into (13) results in (16)
𝐺(𝑠)= 9
20 1+23×10𝑠
1+25×10𝑠+123×10𝑠 (16)
The Bode diagram and step response of the loop transfer function in Equation (16),
without a compensator, are shown in Figure 6 and Figure 7, respectively. Figure 6 indi-
cates that the DC gain is very low (−6.9 dB), leading to a significant static error. Similarly,
the phase margin at the crossover frequency is also low (180° − 165° = 15°), which results
in instability for the system. Figure 7 illustrates that while the seling time is quite good
(57 ms), the maximum overshoot is 84%, which is undesirable. Additionally, the gain
crossover frequency is too low (3.47 kHz) compared to the switching frequency (27 kHz).
These undesirable parameters will be taken into account during the compensator design.
Figure 5. Small signal model of a boost converter.
Figure 6. Bode diagram of converter-2 without a compensator.
Figure 5. Small signal model of a boost converter.
Putting parameters values in (14) and inserting (14) into (13) results in G
T
(s), as given
in (15)
Gvd(s) = 27 1+23 ×10−6s
1+25 ×10−9s+123 ×10−9s2(15)
Inserting the values of Gc(s), H(s) and Gvd(s) into (13) results in (16)
GT(s) = 9
20
1+23 ×10−6s
1+25 ×10−9s+123 ×10−9s2(16)
The Bode diagram and step response of the loop transfer function in Equation (16),
without a compensator, are shown in Figure 6and Figure 7, respectively. Figure 6indicates
that the DC gain is very low (
−
6.9 dB), leading to a significant static error. Similarly, the
phase margin at the crossover frequency is also low (180
◦−
165
◦
= 15
◦
), which results in
instability for the system. Figure 7illustrates that while the settling time is quite good
(57 ms), the maximum overshoot is 84%, which is undesirable. Additionally, the gain
crossover frequency is too low (3.47 kHz) compared to the switching frequency (27 kHz).
These undesirable parameters will be taken into account during the compensator design.
Aerospace 2024, 11, 920 12 of 18
The transfer function of converter-2 is given in (13), utilizing the feedback loop of
converter-1 and -2 𝐺(𝑠)=𝐺(𝑠)𝐺(𝑠)𝐻(𝑠) (13)
where G
T
(s) is the loop transfer function, G
vd
(s) is the control-to-output transfer function,
G
c
(s) is the MPPT block transfer function, and H(s) is the aenuation network transfer
function. In the case of converter-2, H(s) is a voltage divider network with an aenuation
factor of 0.8, while G
c
(s) has a value of 0.25. In order to find G
vd
(s) for converter-2, a small
signal model is drawn, as shown in Figure 5. This model is converted to a transformer
model and all the elements are shifted to the load side. The resultant transfer function of
the G
vd
(s) is given in (14)
𝐺(𝑠)= 𝑉
𝐷󰆒1+𝑠𝐿𝐼
𝑉
1+ 𝐿
𝑅𝐷󰆒𝑠+𝑠𝐿𝐶
𝐷󰆒 (14)
Puing parameters values in (14) and inserting (14) into (13) results in G
T
(s), as given
in (15)
𝐺(𝑠)=27 1+23×10𝑠
1+25×10𝑠+123×10𝑠 (15)
Inserting the values of G
c
(s), H(s) and G
vd
(s) into (13) results in (16)
𝐺(𝑠)= 9
20 1+23×10𝑠
1+25×10𝑠+123×10𝑠 (16)
The Bode diagram and step response of the loop transfer function in Equation (16),
without a compensator, are shown in Figure 6 and Figure 7, respectively. Figure 6 indi-
cates that the DC gain is very low (−6.9 dB), leading to a significant static error. Similarly,
the phase margin at the crossover frequency is also low (180° − 165° = 15°), which results
in instability for the system. Figure 7 illustrates that while the seling time is quite good
(57 ms), the maximum overshoot is 84%, which is undesirable. Additionally, the gain
crossover frequency is too low (3.47 kHz) compared to the switching frequency (27 kHz).
These undesirable parameters will be taken into account during the compensator design.
Figure 5. Small signal model of a boost converter.
Figure 6. Bode diagram of converter-2 without a compensator.
Figure 6. Bode diagram of converter-2 without a compensator.
Aerospace 2024, 11, 920 13 of 18
Figure 7. Step response of converter-2.
2.5. Compensator Design
The compensator must meet the desired requirements of the feedback loop and
effectively remove or at least mitigate the effects of all undesired parameters, such as
ringing, overshoot, low phase margin, and high seling time. To achieve the desired re-
sults in the compensation loop for the proposed design, a PID controller is designed. The
switching frequency of the converter is 55 kHz; therefore, the corner frequency (fc) is set
to one-tenth of the switching frequency (5.5 kHz). To aain a phase margin (θ) of 50°, the
frequencies for the zeros (fz) and poles (fp1 and fp2) should be determined as follows:
𝑓
(𝑠)=
𝑓
1−𝑠𝑖𝑛𝜃
1+𝑠𝑖𝑛𝜃= 1.73 kHz
𝑓
 =
𝑓


1+𝑠𝑖𝑛𝜃
1−𝑠𝑖𝑛𝜃= 17.44 kHz
A higher pole frequency (fp2) is selected 10fc, while the low frequency (fL) of the in-
tegrator is selected less than fc/10. The designed PID compensator is shown in Figure 8,
and the compensator gain (Gc) is given by (17), where Gc is the compensator DC gain
𝐺(𝑠)=𝐺 1+2𝜋
𝑓

𝑠1+ 𝑠
2𝜋
𝑓

1+ 𝑠
2𝜋
𝑓
1+ 𝑠
2𝜋
𝑓
 (17)
Figure 8. Compensator circuit.
The component values of the compensator circuit shown in Figure 8 can be found
from (10), where the frequencies values are already selected in (18).
Figure 7. Step response of converter-2.
2.5. Compensator Design
The compensator must meet the desired requirements of the feedback loop and effec-
tively remove or at least mitigate the effects of all undesired parameters, such as ringing,

Aerospace 2024,11, 920 13 of 17
overshoot, low phase margin, and high settling time. To achieve the desired results in the
compensation loop for the proposed design, a PID controller is designed. The switching
frequency of the converter is 55 kHz; therefore, the corner frequency (f
c
) is set to one-tenth
of the switching frequency (5.5 kHz). To attain a phase margin (
θ
) of 50
◦
, the frequencies
for the zeros (fz) and poles (fp1and fp2) should be determined as follows:
fz(s)=fcr1−sinθ
1+sinθ=1.73 kHz
fp1=fcr1+sinθ
1−sinθ=17.44 kHz
A higher pole frequency (f
p2
) is selected 10f
c
,while the low frequency (f
L
) of the
integrator is selected less than fc/10. The designed PID compensator is shown in Figure 8,
and the compensator gain (Gc) is given by (17), where Gc is the compensator DC gain
Gc(s) = Gc01+2πfL
s1+s
2πfz
1+s
2πfp11+s
2πfp2(17)
Aerospace 2024, 11, 920 13 of 18
Figure 7. Step response of converter-2.
2.5. Compensator Design
The compensator must meet the desired requirements of the feedback loop and
effectively remove or at least mitigate the effects of all undesired parameters, such as
ringing, overshoot, low phase margin, and high seling time. To achieve the desired re-
sults in the compensation loop for the proposed design, a PID controller is designed. The
switching frequency of the converter is 55 kHz; therefore, the corner frequency (fc) is set
to one-tenth of the switching frequency (5.5 kHz). To aain a phase margin (θ) of 50°, the
frequencies for the zeros (fz) and poles (fp1 and fp2) should be determined as follows:
𝑓
(𝑠)=
𝑓
1−𝑠𝑖𝑛𝜃
1+𝑠𝑖𝑛𝜃= 1.73 kHz
𝑓
 =
𝑓


1+𝑠𝑖𝑛𝜃
1−𝑠𝑖𝑛𝜃= 17.44 kHz
A higher pole frequency (fp2) is selected 10fc, while the low frequency (fL) of the in-
tegrator is selected less than fc/10. The designed PID compensator is shown in Figure 8,
and the compensator gain (Gc) is given by (17), where Gc is the compensator DC gain
𝐺(𝑠)=𝐺 1+2𝜋
𝑓

𝑠1+ 𝑠
2𝜋
𝑓

1+ 𝑠
2𝜋
𝑓
1+ 𝑠
2𝜋
𝑓
 (17)
Figure 8. Compensator circuit.
The component values of the compensator circuit shown in Figure 8 can be found
from (10), where the frequencies values are already selected in (18).
Figure 8. Compensator circuit.
The component values of the compensator circuit shown in Figure 8can be found
from (10), where the frequencies values are already selected in (18).
Gco =R2
R1
,fL=1
2πR2Cf2
,fp1=1
2πR1Cin
fp1=1
2πR2Cf1
,fp1=1
2π(R1+R4)Cin
(18)
The Bode plots shown in Figure 9give the complete response of the system after
adding the compensator.
Aerospace 2024, 11, 920 14 of 18
𝐺 =𝑅
𝑅,
𝑓
=1
2𝜋𝑅𝐶,
𝑓
 =1
2𝜋𝑅𝐶
𝑓
 =1
2𝜋𝑅𝐶,
𝑓
 =1
2𝜋(𝑅+𝑅)𝐶 (18)
The Bode plots shown in Figure 9 give the complete response of the system after
adding the compensator.
Figure 9. Bode plot of the system with compensator.
3. Simulation Results
The proposed converter’s performance is demonstrated through both steady-state
and dynamic analyses, as depicted in Figures 10–13. Each figure provides critical insights
into the converter’s operation under different conditions.
Figure 10. Output voltage and current of the proposed converter under steady state.
Figure 11. Ripple comparison of output voltage and current.
0 0.1 0.2 0.3 0.4 0.5 0.6
Time (seco nds)
0
100
200
300
400
Output Current (mA)
Stab ilized output current
under steady state
0 0.1 0.2 0.3 0.4 0.5 0.6
Time (se conds)
0
5
10
15
Output Voltage (V)
Stab ilized output voltage
under ste ady st ate
(a) Output vo ltag
e
(b) Output current
272.6 272.8 273. 0 273.2 273.4
Time (msec)
13.7
13.8
13.9
14
14.1
14.2
14.3
Proposed Converter
Conventional Converter
Output Voltage (V)
(a) Output voltage
225.8
(b) Output current
225.0 225.2 225.4 22 5.6
Time (msec)
360
380
400
420
440
Proposed Converter
Conventional Converter
Output Current (mA)
Figure 9. Bode plot of the system with compensator.

Aerospace 2024,11, 920 14 of 17
3. Simulation Results
The proposed converter’s performance is demonstrated through both steady-state and
dynamic analyses, as depicted in Figures 10–13. Each figure provides critical insights into
the converter’s operation under different conditions.
Figure 10 presents the steady-state output voltage and current profiles. The results
show that the converter maintains stable voltage and current levels under nominal operat-
ing conditions, confirming the system’s reliability. This stable performance is crucial for
satellite missions, where a consistent power supply is essential.
Aerospace 2024, 11, 920 14 of 18
𝐺 =𝑅
𝑅,
𝑓
=1
2𝜋𝑅𝐶,
𝑓
 =1
2𝜋𝑅𝐶
𝑓
 =1
2𝜋𝑅𝐶,
𝑓
 =1
2𝜋(𝑅+𝑅)𝐶 (18)
The Bode plots shown in Figure 9 give the complete response of the system after
adding the compensator.
Figure 9. Bode plot of the system with compensator.
3. Simulation Results
The proposed converter’s performance is demonstrated through both steady-state
and dynamic analyses, as depicted in Figures 10–13. Each figure provides critical insights
into the converter’s operation under different conditions.
Figure 10. Output voltage and current of the proposed converter under steady state.
Figure 11. Ripple comparison of output voltage and current.
0 0.1 0.2 0.3 0.4 0.5 0.6
Time (seconds)
0
100
200
300
400
Output Current (mA)
Stab ilized out put current
under steady state
0 0.1 0.2 0.3 0.4 0.5 0.6
Time (seconds)
0
5
10
15
Output Voltage (V)
Stab ilized out put voltage
under ste ady state
(a) Output vo ltag
e
(b) Output current
272.6 27 2.8 27 3.0 27 3.2 27 3.4
Time (msec)
13.7
13.8
13.9
14
14.1
14.2
14.3
Proposed Converter
Conventional Converter
Output Voltage (V)
(a) Output voltage
225.8
(b) Output current
225.0 225.2 225.4 22 5.6
Time (msec)
360
380
400
420
440
Proposed Converter
Conventional Converter
Output Current (mA)
Figure 10. Output voltage and current of the proposed converter under steady state.
Figure 11 provides a comparison of voltage and current ripples before and after
implementing the proposed converter design. The converter achieves a 20% reduction
in ripple, which is a significant improvement. Reduced ripples directly enhance the
lifespan of connected components, such as batteries, by minimizing stress during charging
and discharging cycles. Additionally, lower ripples allow for the use of smaller passive
components, contributing to a more compact and efficient overall design.
Aerospace 2024, 11, 920 14 of 18
𝐺 =𝑅
𝑅,
𝑓
=1
2𝜋𝑅𝐶,
𝑓
 =1
2𝜋𝑅𝐶
𝑓
 =1
2𝜋𝑅𝐶,
𝑓
 =1
2𝜋(𝑅+𝑅)𝐶 (18)
The Bode plots shown in Figure 9 give the complete response of the system after
adding the compensator.
Figure 9. Bode plot of the system with compensator.
3. Simulation Results
The proposed converter’s performance is demonstrated through both steady-state
and dynamic analyses, as depicted in Figures 10–13. Each figure provides critical insights
into the converter’s operation under different conditions.
Figure 10. Output voltage and current of the proposed converter under steady state.
Figure 11. Ripple comparison of output voltage and current.
0 0.1 0.2 0.3 0.4 0.5 0.6
Time (seconds)
0
100
200
300
400
Output Current (mA)
Stab ilized out put current
under steady state
0 0.1 0.2 0.3 0.4 0.5 0.6
Time (seconds)
0
5
10
15
Output Voltage (V)
Stab ilized out put voltage
under ste ady state
(a) Output vo ltag
e
(b) Output current
272.6 27 2.8 27 3.0 27 3.2 27 3.4
Time (msec)
13.7
13.8
13.9
14
14.1
14.2
14.3
Proposed Converter
Conventional Converter
Output Voltage (V)
(a) Output voltage
225.8
(b) Output current
225.0 225.2 225.4 22 5.6
Time (msec)
360
380
400
420
440
Proposed Converter
Conventional Converter
Output Current (mA)
Figure 11. Ripple comparison of output voltage and current.
Figure 12 illustrates the converter’s dynamic response to an input voltage drop, in-
troduced at 0.2 s. The converter ’s ability to maintain a stable output despite a sudden
input fluctuation showcases its robustness. The swift recovery time with minimal deviation
highlights the converter’s stability, which is critical for spacecraft operations where power
disturbances can arise due to orbital shadowing or other environmental factors.

Aerospace 2024,11, 920 15 of 17
Aerospace 2024, 11, 920 15 of 18
Figure 12. Output voltage and current converter under input voltage drop.
Figure 13. Output voltage and current converter under load variation.
Figure 10 presents the steady-state output voltage and current profiles. The results
show that the converter maintains stable voltage and current levels under nominal oper-
ating conditions, confirming the system’s reliability. This stable performance is crucial for
satellite missions, where a consistent power supply is essential.
Figure 11 provides a comparison of voltage and current ripples before and after
implementing the proposed converter design. The converter achieves a 20% reduction in
ripple, which is a significant improvement. Reduced ripples directly enhance the lifespan
of connected components, such as baeries, by minimizing stress during charging and
discharging cycles. Additionally, lower ripples allow for the use of smaller passive
components, contributing to a more compact and efficient overall design.
Figure 12 illustrates the converter’s dynamic response to an input voltage drop, in-
troduced at 0.2 s. The converter’s ability to maintain a stable output despite a sudden
input fluctuation showcases its robustness. The swift recovery time with minimal devia-
tion highlights the converter’s stability, which is critical for spacecraft operations where
power disturbances can arise due to orbital shadowing or other environmental factors.
Figure 13 presents the system’s response to load variations introduced at 0.2 s and
0.5 s. The results demonstrate that the converter effectively restores the output voltage to
the desired setpoint with minimal overshoot and fast seling time. This quick response is
essential for maintaining power quality in the face of variable loads, further proving the
converter’s capability to handle dynamic operational conditions reliably.
The results in Figures 10–13, along with the performance metrics summarized in
Table 1, validate the effectiveness of the proposed converter design. With 2% voltage
ripple, <7.5% current ripple, and 2.5% voltage overshoot, the converter’s performance
surpasses typical industry requirements, making it suitable for reliable nanosatellite
missions.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Time (seconds)
0
2
4
6
8
10
12
14
16
Output Voltage (V)
Load increase
to do uble
Load decrease
back to half
(a) Output voltage
0 0.1 0.2 0. 3 0. 4 0.5 0.6 0. 7
Time (seconds)
0
50
100
150
200
250
300
350
400
Output Current (mA)
Load increase
to do uble
Load decrease
back to half
(b) Output current
Figure 12. Output voltage and current converter under input voltage drop.
Figure 13 presents the system’s response to load variations introduced at 0.2 s and
0.5 s. The results demonstrate that the converter effectively restores the output voltage to
the desired setpoint with minimal overshoot and fast settling time. This quick response is
essential for maintaining power quality in the face of variable loads, further proving the
converter’s capability to handle dynamic operational conditions reliably.
Aerospace 2024, 11, 920 15 of 18
Figure 12. Output voltage and current converter under input voltage drop.
Figure 13. Output voltage and current converter under load variation.
Figure 10 presents the steady-state output voltage and current profiles. The results
show that the converter maintains stable voltage and current levels under nominal oper-
ating conditions, confirming the system’s reliability. This stable performance is crucial for
satellite missions, where a consistent power supply is essential.
Figure 11 provides a comparison of voltage and current ripples before and after
implementing the proposed converter design. The converter achieves a 20% reduction in
ripple, which is a significant improvement. Reduced ripples directly enhance the lifespan
of connected components, such as baeries, by minimizing stress during charging and
discharging cycles. Additionally, lower ripples allow for the use of smaller passive
components, contributing to a more compact and efficient overall design.
Figure 12 illustrates the converter’s dynamic response to an input voltage drop, in-
troduced at 0.2 s. The converter’s ability to maintain a stable output despite a sudden
input fluctuation showcases its robustness. The swift recovery time with minimal devia-
tion highlights the converter’s stability, which is critical for spacecraft operations where
power disturbances can arise due to orbital shadowing or other environmental factors.
Figure 13 presents the system’s response to load variations introduced at 0.2 s and
0.5 s. The results demonstrate that the converter effectively restores the output voltage to
the desired setpoint with minimal overshoot and fast seling time. This quick response is
essential for maintaining power quality in the face of variable loads, further proving the
converter’s capability to handle dynamic operational conditions reliably.
The results in Figures 10–13, along with the performance metrics summarized in
Table 1, validate the effectiveness of the proposed converter design. With 2% voltage
ripple, <7.5% current ripple, and 2.5% voltage overshoot, the converter’s performance
surpasses typical industry requirements, making it suitable for reliable nanosatellite
missions.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Time (seconds)
0
2
4
6
8
10
12
14
16
Output Voltage (V)
Load increase
to do uble
Load decrease
back to half
(a) Output voltage
0 0.1 0.2 0. 3 0.4 0. 5 0.6 0.7
Time (seconds)
0
50
100
150
200
250
300
350
400
Output Current (mA)
Load inc rease
to do uble
Load decrease
back to half
(b) Output current
Figure 13. Output voltage and current converter under load variation.
The results in Figures 10–13, along with the performance metrics summarized in
Table 1, validate the effectiveness of the proposed converter design. With 2% voltage ripple,
<7.5% current ripple, and 2.5% voltage overshoot, the converter’s performance surpasses
typical industry requirements, making it suitable for reliable nanosatellite missions.
Table 1. Typical requirement vs. achieved results.
Parameter Requirement Achieved Result
Voltage ripple up to 5% of output voltage 2%
Current ripple 10% to 20% of load current 7.5%
Voltage overshoot
under load change 10% to 20% of output voltage 2.5%
4. Conclusions
This paper presents the development and analysis of a high-performance interleaved
converter with a constant voltage MPPT technique tailored for small satellites. The con-
verter is engineered to deliver a consistent output voltage while effectively managing
solar panels at the MPPT to accommodate a broad input range. To enhance reliability and
mitigate the risks associated with single-component failures in miniaturized satellites, the
design is executed using aerospace-grade components.

Aerospace 2024,11, 920 16 of 17
Detailed analyses of the converter’s loop transfer function using a Bode diagram
revealed that the initially designed converter, lacking a compensation network, exhibited
suboptimal performance in terms of gain, phase margin, and settling time. To address
these shortcomings, a PID compensator was devised and integrated into the system’s loop.
This integration yielded significant improvements, showcasing notably higher gain and
substantially enhanced phase margin. The Bode diagram analysis highlighted a marked
increase in the gain margin, while the phase margin exhibited significant enhancements at
the crossover frequency.
Ultimately, the proposed interleaved converter not only minimizes output ripples but
also enhances the reliability of passive components, thereby extending the lifespan of the
onboard battery. The streamlined design and reduced component count contribute to a
more compact satellite configuration, aligning with the objective of reducing the satellite’s
overall size and weight.
Author Contributions: Conceptualization, S.A.K. and A.A.; methodology, A.A.; software, M.T.;
validation, Z.T.; formal analysis, S.A.K.; investigation, Z.T.; resources, Z.T.; data curation, M.T.;
writing—original draft preparation, S.A.K.; writing—review and editing, Z.T.; visualization, A.A.;
supervision, Z.T.; project administration, Z.T. All authors have read and agreed to the published
version of the manuscript.
Funding: This research received no external funding.
Data Availability Statement: The original contributions presented in the study are included in the
article, further inquiries can be directed to the corresponding author.
Conflicts of Interest: The authors of this journal paper declare that they have no financial or personal
affiliations that could potentially influence or bias the content or findings presented in this manuscript.
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