A 3.3 V 14-bit 10 MSPS calibration-free CMOS pipelined A/D converter

Conference Paper · February 2000with14 Reads
DOI: 10.1109/ISCAS.2000.857124 · Source: IEEE Xplore
Conference: Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on, Volume: 1

A calibration-free 3.3 V 14-bit 10 MSPS pipelined analog-to-digital (A/D) converter was implemented using a 0.35 μm CMOS technology. The ADC utilizes a 4-stage pipelined architecture with a wideband sample and hold amplifier and achieves the highest resolution reported to date at 3.3 V 10 MHz. The proposed hybrid capacitor switching technique of one/two feedback capacitors is applied to improve the linearity which is limited by component mismatch depending on the process. Since the proposed technique can be implemented by simple circuit compared with previous self-calibration techniques, it allows smaller area and lower power consumption. The A/D converter occupies a die area of 2.43 mm<sup>2</sup> (1800 μm*1350 μm) and dissipates 118 mW at a 10 MHz clock rate with a 3.3 V single supply voltage in measurement results. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.73 LSB and ±1.55 LSB, respectively