Conference Paper

A scalable MPEG-4 video codec architecture for IMT-2000 multimedia applications

Toshiba Corp., Kawasaki
DOI: 10.1109/ISCAS.2000.856290 Conference: Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on, Volume: 2
Source: IEEE Xplore


A scalable MPEG-4 video codec architecture is proposed to achieve
low power consumption and high cost-effectiveness for IMT-2000
multimedia applications. The MPEG-4 video codec consists of a 16-bit
multimedia-extended RISC processor and dedicated hardware accelerators,
which bring about both low power consumption and programmability. The
proposed architecture is extended and applied for the development of two
MPEG-4 LSIs. One is an MPEG-4 video codec LSI, which performs an MPEG-4
video encoding and decoding at 15 frames per second with quarter common
intermediate format. The other is an MPEG-4 audiovisual LSI, containing
three 16-bit RISC processors and a 16-Mbit embedded DRAM, executes the
major functions of 3GPP 3G-324M video telephony for IMT-2000
applications. By introducing the optimization of the embedded DRAM
configuration, clock gating technique, and low power motion estimation,
the MPEG-4 audiovisual LSI consumes only 240 mW when it activates MPEG-4
video SP@L1 codec, the AMR speech codec, and the H.223 annex B multiplex
at 60 MHz clock rate

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    • "Advances in MPEG4 video standard development has resulted in complex SoCs which features a high logic density and a large number of pins. They consist of many dedicated hardware processing cores [1] [2] [3] such as a Discrete Cosine Transform (DCT), Inverse DCT (IDCT), Variable Length Coding (VLC), Quantizer (Q), inverse-Quantizer (IQ), Motion Compensator (MC) and Motion Estimator (ME) etc., which possess many different functions. "
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    ABSTRACT: This paper introduces a specific architecture including an infrastructural IP for functional verification and diagnostics, which is suitable for functional core-based testing of an MPEG4 SoC. Our advanced MPEG4 SoC results in a high complexity SoC with limited physical access to many different functional cores. The proposed test method provides direct monitoring and control for each core, which enables core verification at actual speed. It significantly decreases the verification time due to the large number of required test vectors in typical MPEG4 verification. Furthermore, it also makes the system scalable for functional core expansion due to upgrading of standards. The proposed infrastructural IP is also linked to PC-based interactive tools to simplify the verification of individual and integrated cores. It also provides detailed diagnostic data that enables simple system debugging. The debugging tools also feature test-pattern generation and simulation of expected values. Actual system implementation has shown full functionality of our proposed method.
    Full-text · Article · Dec 2009 · ITB Journal of Information and Communication Technology
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    • "Further, a 250-MHz SPXK5 will possess the processing power required for both the video codec and speech codec, and it will consumes 50 mW at 0.9 volts. Let us compare power consumption between a dedicateddesign approach and our programmable-DSP approach for MPEG- 4. The dedicated MPEG-4 video codec LSI reported in [6] consumes 240 mW at 60-MHz clock frequency when it executes both SP@L1 video codec and speech codec. The power consumption of 250-MHz SPXK5 is dramatically lower than that of the dedicated MPEG-4 LSI, where a 250-MHz SPXK5 can handle both SP@L2 video codec and speech codec. "
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    ABSTRACT: We have developed a new-generation, general-purpose digital signal processor (DSP) core with low power dissipation for use in third-generation (3G) mobile terminals. The DSP core employs a 4-way VLIW (very long instruction word) approach, as well as a dual-multiply-accumulate (dual-MAC) architecture with good orthogonality. It is able to perform both video and speech codec for 3G wireless communications at 384 k bit/sec with a power consumption of approximately 50 mW. This paper presents an overview of both the DSP core architecture and a DSP instruction set, and it also gives some application benchmarks
    Full-text · Conference Paper · Feb 2001
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