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Miniaturized Broadband Quadrature Coupler at Millimeter-Wave Band
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The proliferation of millimeter-wave (mmWave) bands across 24–90 GHz and the strict spectral efficiency requirements demand future transmitter front ends to operate across multiple bands with simultaneously back-off efficiency and high linearity—characteristics that typically trade off strongly with each other. In this article, we propose a simultaneously broadband, back-off efficient and linear mmWave Doherty power amplifier (PA) architecture with a quadrature hybrid, and a non-Foster inspired impedance tuner on-chip. The combination of transformer-based hybrid and the quasi-non-Foster tuner allows the architecture to synthesize optimal impedances to the PA across the 2-D variations of power back-off and frequency, enabling high back-off efficiency across a broad frequency range. In addition, the unique location of the tuner at the isolation port of the hybrid allows us to exploit its benefits while shielding the architecture from effects of tuner non-linearity, power losses, and typical stability concerns of traditional non-Foster circuits. For high linearity, we implement an emitter follower-based class-C bias network with boosting effect. The PA is implemented in a 130-nm SiGe BiCMOS process. Across 44–64 GHz, the PA achieves 18.5–21.5-dBm
, the peak collector efficiency of 26%–34.7% and 14%–23.2% at 6-dB back-off, maintaining back-off enhancement ratio of 2.77/2.53/2.37 (1.39/1.27/1.19) at 46/52/62 GHz compared to the class-A (class-B) operation. It supports 6-gigabit-per-second (Gb/s) 64-QAM signal with −26.5-dB/−28.3-dBc error vector magnitude (EVM)/adjacent channel leakage ratio (ACLR) at average
/power added efficiency (PAE) of 14.6 dBm/15% at 54 GHz. This work achieves the state-of-the-art bandwidth among silicon-based mmWave PAs where higher than class-B back-off efficiency is achieved.
This article focuses on the design of high-performance coupled slow-wave coplanar waveguide (CS-CPW) in CMOS technologies for the millimeter-wave (mm-wave) frequency bands. First, the theory as well as the electrical model of the CS-CPW are presented. Next, the analytical approach for the calculation of the model parameters is discussed. Then, by using the developed model, two mm-wave backward directional 3-dB couplers are designed in a bipolar complementary metal-oxide-semiconductor (BiCMOS) 55-nm technology for 120- and 185-GHz operation, respectively. Simulation and experimental results demonstrate that the use of the CS-CPW concept leads to state-of-the-art performance, with a good agreement between the analytical model, electromagnetic simulations, and measurement results.
In this letter, a new 90° coupler with a symmetric coupled-line structure featuring the use of the tuning multiple floating metals technique is designed, analyzed, and verified for subterahertz (THz) applications; this new coupler was fabricated on the standard Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-
1P6M CMOS process. With the proposed structure, the impedances of even and odd modes can be designed individually to simultaneously optimize the performance in terms of insertion loss, phase balance, amplitude balance, isolation, and reflection coefficients. The bandwidths of phase imbalance (±3°) and amplitude imbalance (±1 dB) are 162 and 100 GHz, respectively. Reflection coefficients less than −20 dB are reached at 0.2–184 GHz, and isolation higher than 20 dB is from 0.2 to 200 GHz.
In this letter, we have presented a design of on-chip millimeter-wave 3-dB quadrature coupler that utilizes the coupled slow wave coplanar waveguide. The designed CMOS coupler covers the whole E- and W-band and occupies a silicon area of only 0.0115 mm
2
, which is significantly smaller compared to the conventional microstrip-line-based Lange couplers. Measurement of the quadrature coupler shows a -3.5 dB through and a -4.4-dB coupling at 90 GHz. A less than ±1-dB amplitude and a ±4° phase errors from 55 to 110 GHz are recorded.
A compact and wideband coupler for the 60-GHz frequency band applications using 65-nm CMOS technology is presented. By meandering the coupled line, a miniaturized coupler can be obtained. The proposed coupler achieves a measured insertion loss between the input port and the through port (S
21
) of 6.3 dB and between the input port and the coupled port (S
31
) of 5.6 dB at 60 GHz. The measured amplitude imbalance and phase difference are 0.75 dB and 92°, respectively, at 60 GHz. Overall, the proposed coupler can achieve a measured amplitude imbalance of <;1 dB, phase imbalance of <;4°, return loss, and isolation better than 13 and 20 dB, respectively, from 50 to 67 GHz. In addition, the proposed coupler occupies a core area of only 156 μm × 157 μm (0.024 mm
2
).
This letter proposes a compact and broadband quadrature coupler with a center frequency of 55 GHz, which consists of a 90° broadside coupled-line to support the differential signal propagation and two T-type L-C networks to support the common signal propagation. To analyze the proposed coupler, an equivalent circuit model is provided for estimation of the distributed and lumped component values. The measured results of the proposed on-chip quadrature coupler show that the return loss and isolation are greater than 20 dB with a bandwidth of 105%, while the insertion loss is about -0.85 dB. The magnitude imbalances are less than 1 dB within the bandwidth of 56% and the phase differences are with ±1° errors within the bandwidth of 96.9%. The chip size, excluding the test pads, only 0.31 × 0.22 mm
2
.
Load-variation insensitivity, for impedance matching between power amplifiers (PAs) and transmitting antennas, contributes to challenging the design of millimeter-wave wireless systems. In this paper, a W-band two-way balanced PA based on a compact quadrature coupler with a broadside coupled stripline (BCSL) as the core is presented to enhance the load-variation insensitivity and stability. The proposed coupler is truly broadband with low amplitude and phase imbalance. The proposed W-band balanced PA achieves higher power-added efficiency (PAE) and unsaturated output power sat over wide frequency bandwidth. The W-band balanced PA is implemented in a 0.13-μm SiGe BiCMOS process and achieves a measured sat of 16.3 dBm and a peak PAE of 14.1% at 100 GHz (with 1.6-V power supply). The measured sat with 1-dB bandwidth is from 91 to 102 GHz. The measured results present the feasibility of the compact quadrature coupler. The total chip surface area (with pads) is 0.64 mm
2
, where the size of the proposed quadrature coupler area is only 0.04 mm2.
This paper presents a transformer-based poly-phase network to generate fully differential quadrature signals with low loss, compact area, and high-precision magnitude and phase balance over an ultra-wide bandwidth. A fully differential high-coupling 8-port folded transformer-based quadrature hybrid serves as the basic building block for the poly-phase unit stage to achieve significant size reduction and low loss. Multiple poly-phase unit stages can be cascaded to form the multistage poly-phase network to substantially extend the quadrature signal generation bandwidth. The designs of the high-coupling transformer-based quadrature hybrid, the poly-phase unit stage, and the multistage transformer-based poly-phase network are presented with the closed-form design equations in this paper. As a proof-of-concept design, a 3-stage transformer-based poly-phase network is implemented in a standard 65 nm bulk CMOS process with a core area of 772 μ m × 925 μ m. Measurement results of this poly-phase network over 3 independent samples demonstrate that the output In-Phase and Quadrature (I/Q) magnitude mismatch is less than 1 dB from 2.8 GHz to 21.8 GHz with a passive loss of 3.65 dB at 6.4 GHz. The measured output I/Q phase error is less than 10 ° from 0.1 GHz to 24 GHz. The effective Image Rejection Ratio (IRR) based on the measured I/Q balancing is more than 30 dB from 3.7 GHz to 22.5 GHz. The 3-stage transformer-based poly-phase network design achieves high-quality quadrature signal generation over a first-ever one-decade bandwidth together with low-loss and compact area.
This work presents a highly integrated transmitter (TX) and receiver (RX) chipset operating from 50 to 100 GHz. The local oscillator (LO) is realized using a high output power millimeter-wave integrated frequency synthesizer with an octave output frequency range. The proposed low-complexity discrete tuned synthesizer architecture employs a single wide-tuning range voltage-controlled oscillator core and a single-sideband mixer, which can be switched to operate as a LO amplifier. An ultra broadband variable gain amplifier, with a gain control range , is used at the output of the synthesizer to provide a tunable output power. A maximum output power from to and an output phase noise from to at 1-MHz offset are measured over the complete output frequency range. Moreover, a spurious suppression is achieved over the entire synthesizer's tuning range. The RX shows a conversion gain and a noise figure from 50 to 100 GHz. The TX's measured saturated output power is from to over the entire frequency range. The complete chipset is realized in a commercial low-cost SiGe:C technology with an of . Each of the TX and RX chips including the frequency synthesizers draw a current of 370 mA from a 3.3-V supply.
This paper presents compact CMOS quadrature hybrids by using the transformer over-coupling technique to eliminate significant phase error in the presence of low- Q CMOS components. The technique includes the inductive and capacitive couplings, where the former is realized by employing a tightly inductive-coupled transformer and the latter by an additional capacitor across the transformer winding. Their phase balance effects are investigated and the design methodology is presented. The measurement results show that the designed 24-GHz CMOS quadrature hybrid has excellent phase balance within plusmn0.6deg and amplitude balance less than plusmn 0.3 dB over a 16% fractional bandwidth with extremely compact size of 0.05 mm2. For the 2.4-GHz hybrid monolithic microwave integrated circuit, it has measured phase balance of plusmn0.8deg and amplitude balance of plusmn 0.3 dB over a 10% fractional bandwidth with a chip area of 0.1 mm2 .
This paper presents artificial-synthesized edge- coupled transmission lines (TLs) based on complementary metal- oxide semiconductor (CMOS) technology. The artificial coupled- line (CL), the so-called the complementary-conducting-strip coupled line (CCS CL), consists of the unit cell and is meandered in the 2-D plane. The unit cell, whose dimensions are much smaller than the guiding wavelength at the operating frequency, provides five structural parameters for CL syntheses. The synthesized CLs, which are fully characterized by using theoretical and experimental procedures, reveal the following unique guiding properties. First, the coupling coefficient (K) can be 7.7% higher than that of the meandered conventional edged-coupled TLs. Second, the even- and odd-mode propagation constants can be synthesized as identical at the same time. Two backward-wave directional couplers for achieving the tight coupling and high directivity are designed by incorporating artificial CCS CL. Two prototypes are fabricated by the standard 0.18-??m CMOS technology, occupying the chip areas of 120.0 ??m ?? 240.0 ??m. The measured results show that the isolation is higher than 25.0 dB from 10.0 to 40.0 GHz with a coupling of 14.4 dB. On the tight coupler design, the through and coupling are 4.65 ?? 0.15 dB from 30.0 to 40.0 GHz with an amplitude imbalance of less than 0.3 dB.
In this paper, an improved method of determining the
primary-to-secondary coupling capacitance for planar spiral transformers
(PST's) is presented, which enhances previous work. A more general
monolithic microwave integrated circuit (MMIC) compatible lumped element
multisection model is also presented based on symmetric-width uniformly
coupled transmission lines. These techniques were developed to design a
90° hybrid as a MMIC with a center frequency of 2.5 GHz. The design
was frequency scaled to 0.5 GHz and fabricated in the microwave
integrated circuit (MIC) for verification. Producibility is enhanced and
coupling is effectively increased with the novel use of series
capacitors which cancel some of the self-inductance of the transformers.
Measured results are presented for both a quadrature hybrid and the
individual PST used in the quadrature hybrid. The measured results show
excellent agreement with the computer models
We have derived a lumped-element circuit from its coupled line counterpart for a quadrature hybrid coupler. We discuss the uses, design, and characteristics of such circuits in CMOS technology. We show measured characteristics of an example 50-Ω 2-GHz coupler with 65 dB of image rejection, 22 dB of directivity, and a 4.7-dB noise figure.
Rf and microwave coupled-line circuits
- R Mongia
- I J Bahl
- P Bhartia
Rf and microwave coupled-line circuits
- Mongia