To save memory, layout-to-circuit extractors that use the Finite-Element Method for resistance extraction usually solve the corresponding set of equations with a frontal solution method. We show that this method is inefficient when used with a scanline ordering of the elements. As an improvement, we introduce the Delayed Frontal Solution algorithm, which allows us to replace the scanline ordering
... [Show full abstract] by the minimumdegree ordering. Thus, extraction times are reduced with more than one order of magnitude at a small cost of extra memory. 1 Introduction The values of the interconnect resistances in modern integrated circuits tend to increase. This is caused by the fact that, due to down-scaling, the widths of the wires are decreased. Also, due to the increase in chip size, the average length of the wires increases. Significant values for interconnect resistances in integrated circuits may cause malfunctioning of the circuit, e.g. because of too large delay time values or because of too great ...