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Adder based digital control block for analog front end in biomedical applications
Abstract
High-speed, efficient, and reliable processing unit at a reasonable cost is critical in microprocessor design. This analysis concentrates on enhancing the Ripple carry adder (RCA), recognized for its high-performance operation because of transistor count, power consumption, delay, and required energy. This work describes and 9-bit RCA, building from the proposed 1-bit adder and AND gate with two inputs. The proposed adder acquires an average power deduction of 30%–98%, a delay reduction of 80%–99%, and a decrement of 58%–99% power delay product (PDP) than outperforming existing adder circuits. It enables the addition of a 9-bit adder with control from the logic circuit. Experimental results indicate notable improvements in the delay of 80%–99% and 15%–54.6% of power dissipation compared to previous Adder designs for higher bits. Also, a digital control block (DCB) has designed from proposed adder designs with optimized delay and power. It enhances the function of DCB with the improvement of all circuits of DCB.
This research addresses the critical need for robust security in embedded systems, particularly within the Internet of Medical Things. We propose an integrated framework combining advanced masking algorithms and post-quantum cryptography to mitigate side-channel and quantum threats. The framework incorporates an Artificial Intelligence based health monitoring model using Internet of Things devices for real-time patient data analysis, enabling timely and accurate medical decision-making. The approach ensures enhanced data integrity, confidentiality, and practical viability through rigorous evaluation of execution time, power efficiency, and randomness tests. This resilient system lays a foundation for secure and adaptive healthcare technologies, safeguarding IoMT ecosystems against evolving cyber threats.
An operational trans-conductance amplifier (OTA) is a fundamental component of electronic appliances. This paper introduces a novel design of OTA for minimal power, low voltage applications. The proposed OTA comprises an ultra low power current mirror design with enhanced bandwidth. The proposed OTA circuit is operated at 0.8V, contributing input noise of 26.33nV/(Hz)1/2 with a power of 29.52μW. The additional parameters of new OTA are DC gain (87.32dB), common mode rejection ratio (145.47dB), gain bandwidth (4.73MHz), phase margin (36.56∘). These figures are significantly improved as compared to conventional OTAs. Analog-to-digital convertor (ADC) is also designed as an application of the proposed OTA. The improvements offered by ADC in terms of power and bandwidth are also compared with state of the art.
Memristor can store calculation results while computing, and utilizing memristor to realize in-memory computing is considered as one of the potential methods to break the bottleneck of Von Neumann architecture. To construct high performance computing systems, it is necessary to design memristor-based computing units with great advantages in delay, area, and integratability. This brief presents a high speed memristor-based
N
-bit ripple carry adder (RCA), with special design to facilitate the implementation with 1T1R arrays. After carries are calculated and aligned efficiently, we adopt Memristor-Aided LoGIC (MAGIC) to calculate and store the outputs of RCA in parallel, where The proposed
N
-bit RCA only consists of
5N+1
memristors,
8N+1
MOSFETs, and its delay is
N+4
. Compared with the existing memristive RCA, the proposed RCA has great advantage in delay, while it is easy for integration in 1T1R array.
Adders are one of the essential blocks of Arithmetic Logic Unit (ALU), addressing the memory, table indices and many more such types of applications. The speed of the adder unit more often decides the performance of CPU (Central Processing Unit) and GPU (Graphics Processing Unit) for graphics applications. The high-speed design is a very important performance parameter speed that too with less implementation area and low power consumption. In this paper, the author proposes a novel 32-bit Residue Hybrid Adder (RHA) using the Residue Number System (RNS) and implemented using a Hybrid CMOS/PTL logic style. An RNS has the advantage of representing a large integer using a set of few smaller integers to make computation more efficient and effective. On the other side, parallel prefix adders provide faster execution time as it performs the operation in parallel. With our paper, it is evident that RHA gives better performance in terms of delay, power consumption and area for arithmetic operations. The experimental analysis has been performed using the EDA tool on 45-nm CMOS technology. The power, delay and power delay product (PDP) performance parameters are compared with the existing adders and the results show that, thanks to smaller modules, proposed units have both smaller area and delay by up to 45% and 41%, and, consequently, they allow achieving up to over 46% power saving, respectively.
As traditional ultrasonic imaging systems (UIS) are expensive, bulky, and power-consuming, miniaturized and portable UIS have been developed and widely utilized in the biomedical field. The performance of integrated circuits (ICs) in portable UIS obviously affects the effectiveness and quality of ultrasonic imaging. In the ICs for UIS, the analog-to-digital converter (ADC) is used to complete the conversion of the analog echo signal received by the analog front end into digital for further processing by a digital signal processing (DSP) or microcontroller unit (MCU). The accuracy and speed of the ADC determine the precision and efficiency of UIS. Therefore, it is necessary to systematically review and summarize the characteristics of different types of ADCs for UIS, which can provide valuable guidance to design and fabricate high-performance ADC for miniaturized high resolution UIS. In this paper, the architecture and performance of ADC for UIS, including successive approximation register (SAR) ADC, sigma-delta (Σ-∆) ADC, pipelined ADC, and hybrid ADC, have been systematically introduced. In addition, comparisons and discussions of different types of ADCs are presented. Finally, this paper is summarized, and presents the challenges and prospects of ADC ICs for miniaturized high resolution UIS.
As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50–70% when compared to IMPLY, NAND, NOR and other similar logic primitives.
Nowadays, arithmetic computing is an important subject in computer architectures in which the one-bit full-adder gate plays a significant role. Thus, efficient design of such full-adder component can be beneficial to the overall efficiency of the entire system. In this essay, a novel method for the design and simulation of a combined majority gate toward realization of the one-bit full-adder gate is proposed. We inspect an alternative approach for the streamlined physical design of quantum-dot cellular automata (QCA) full-adder circuits in which the placement of input cells and wire crossing congestion are substantially reduced. The proposed method has outstanding characteristics such as low complexity, reduced area consumption, simplified physical design, and ultra-high speed one-bit full-adder. Based on simulation results the proposed design provides 33.33% reduction in area and 20.00% improvement in complexity as well as 10.49% in 1 Ek reduction in power consumption.
Quantum-dot cellular automata (QCA) is among the most promising nanotechnologies as the substitution for the current metal oxide semiconductor field effect transistor based devices. Therefore, lots of attentions have been paid to different aspects to improve the efficiency of QCA circuits. In this way, the adder circuits are widely investigated since their performance can directly affect the whole digital system performance. In this paper, a new ultra-high-speed QCA full adder cell is proposed based on multi-layer structures. The proposed full adder cell is simple in design using 3-input Exclusive-OR (TIEO), which computes the Sum bits and Majority gate, which computes the Carry bits. To verify the efficacy of the presented full adder cell, it is considered, the main constructing block in a 4-bit ripple carry adder circuit. Hence, we have achieved significant improvements in terms of area and cell count. Particularly simulation results show a 20% and 1.8% reduction respectively in the area and cell count overhead. Detailed performance evaluation and structural analysis are performed in different aspects to authenticate the proposed circuits (one-bit and 4-bit) having superb performance in comparison to previously reported works. QCADesigner CAD tool has been used to verify the correct functionality
of the proposed architectures.
Memristor based digital logic circuits open new pathways for exploring advanced computing architectures, which provide a promising alternative to conventional IC technology. In several memristor based logic design methods, the memristor ratioed logic (MRL) is compatible with traditional CMOS technology. Two kinds of carry-lookahead adders (CLA) based on the hybrid CMOS-memristor structure are proposed, within which one is based on MRL logic, and the other is an improved one that is implemented by MRL universal gate (MRLUG). The proposed CLAs are verified by theoretical analyses and simulations, showing that the proposed design method requires fewer memristors and CMOSs than the IMP-based or CMOS-based CLAs, which means smaller circuit size and lower power consumption.
We have proposed a modified Carry Select Adder (CSLA) structure which uses a parallel prefix structure with Binary to Excess – 1 converter (BEC). The proposed adder has been compared with Conventional, BEC, Brent – Kung (BK), Ladner – Fischer (LF) and Kogge – Stone (KS) based CSLA in terms of area, power consumption and performance. The proposed CSLA shows a significant decrease in the area and power compared to KS based CSLA. Particularly, the proposed CSLA structure exhibit significant improvement in speed by 54.41%, 7.95%, 7.82% to Conventional CSLA, 65.75%, 24.65%, 21.61% to BEC-CSLA, 50.79%, 13.83%, 9.30% to BK-CSLA, 43.12%, 8.99%, 5.35% to LF-CSLA, 44.64%, 10.50%, 6.30% to KS-CSLA for 4 bit, 8 bit and 16 bit respectively. All the CSLA structures are designed using Verilog HDL, simulations and synthesis have been performed in Cadence tool using 0.18 µm CMOS technology.
Biomedical devices have enormous possibilities in health applications. A low-noise amplifier (LNA) is a crucial circuit in neural recording, ECG, and EEG systems. The performance of LNAs has to vary with the characteristics of their different components. This contribution presents an empirical comparison between the latest state-of-the-art LNAs in health applications. Using the specter tool of MOS technology, LNAs have implemented at 180, 90, and 65 nm and simulated at a wide supply voltage (1–1.8 V) range. There are 99.9% power variation, 103.7% bandwidth range, 93.18% gain range, 91.17% noise figure vary, and IIP3 97.5% area variation for different LNA designs. Different LNAs have used in analog front end (AFE) design/circuits. A comparison of AFE designs has shown that there are 85.07% power saving, 79.78% maximal bandwidth, and 93.54% best performance.KeywordsLow-noise amplifier (LNA)Analog front end (AFE)GainCurrent reuse techniquesNoise cancelation techniquesOperational trans-conductance amplifier (OTA)Noise figure (NF)
This work introduces an active feedback structure into the Inverter Cascode Trans-Impedance amplifier design, allowing the enhanced circuit to achieve a reasonable 32 and 84 times improvement in bandwidth and power consumption respectively over the traditional circuit of Inverter Cascode Trans-Impedance amplifier utilizing resistor as feedback mechanism. The gain of the proposed enhancement circuit was determined to be 53.2 dB, with 9.2 GHz bandwidth and 3.2 mW of power consumption, hence the proposed design is appropriate for broad bandwidth applications designed to operate with low supply voltage.
5G-distinctive network control systems of the existing automated guided vehicles are likely to bring immense improvement in the performance using fifth generation of mobile communication (5G) technology. Recent days 5G communication systems are having requirement of FIR Filter having auto-adjustment of bandwidth. In the conventional finite impulse response filters, once the design is completed, we cannot change the frequency band. Thus, in auto adjustment frequency selective FIR filters to get desired bandwidth many filter coefficients are required. For implementation of field programmable gate array (FPGA). This generates a huge amount of slice. In this paper a control logic to choose different finite impulse response filters with set of coefficients based on clock signal, selects a finite impulse response filter resulting in frequency selectivity. The proposed design is to implement RFIR filter based on partial product having control logic to achieve better bandwidth needs with auto adjustment of frequencies. Filter order is used as 16. Area of overall designs is reduced by use of partial product in the FIR filter. The overall power consumed is 155 mw. Power consumption is reduced by 12.4%. Utilized area is reduced as compared to folded as well as unfolded direct form of FIR filter. Also, delay is reduced by 27.2% having value as 1.409 ns. The simulation outcomes of the design are validated through Xilinx ISE on virtex-7 FPGA.
This research proposes a novel, low-cost, real-time framework for timely detection of the onset of quality deterioration of fruits and vegetables during storage and transit in India. This solution aims to enable timely consumption of the same before they perish. Maintenance of in-transit freshness of fruits and vegetables is a complex biological process. We propose to monitor the same through a smart IoT based framework that will estimate real-time data regarding the temperature of food items during transport. Thus real-time, continuous, in-transit monitoring and assessment shall aid in assessing the appropriate delivery time for fruits and vegetables. To enable large-scale implementation of the framework open-source, affordable solutions have been utilized to keep the framework simple, adaptable, and low cost.
Quantum Dot Cellular Automata (QCA) technology is gaining popularity for its low power requirements, high speed and efficient miniaturization of digital circuits. Especially, digital circuits now need to be realized and investigated at quantum levels. The manuscript presents the design of several combinational and sequential logic circuits by employing reversible quantum gates such as Peres gate, Thapliyal Ranganathan (TR) gate and Feynman gate (FG) using QCA technology. The manuscript presents the novel design of various latches (D, T, JK and SR) using Feynman gate. The manuscript also demonstrates the design of reversible one-bit magnitude comparator, half & full subtractors, half adder using reversible logic gates employing less number of quantum cells. A comparison of obtained results show that published cell count for different latch designs using various reversible gates is significantly higher than proposed latch deigns using Feynman gate. This demonstrates that the proposed designs are more suitable to reduce hardware cost, and hence leading to better power usage and space optimization. Also, few of these digital circuits have been implemented and analyzed in terms of look up tables (LUTs), number of slices and delay using complementary-metal–oxide–semiconductor (CMOS) technology on system Verilog. In addition, the proposed circuits have been compared with the existing work in terms of cell count, area and delay.
A multi-channel time-division multiplexing (TDM) analog front end (AFE) with low mismatch and high input impedance for bio-sensors is proposed. To reduce mismatches among channels, a four-channel synchronous DC offset elimination system based on TDM technology is proposed, which can multiplex both the low-noise amplifier (LNA) and the variable gain amplifier (VGA). An input impedance boosting technology based on differential difference amplifier (DDA) is proposed to increase the equivalent input impedance of the AFE. The proposed improved digital-controlled DC-servo loop (DCDSL) is applied to four-channel synchronous calibration, which realizes the multiplexing of the first-stage amplifier, solves the problem of the comparator misjudgment, and breaks through the limitation of the channel numbers. The circuit is implemented in
CMOS process. The core area and power of each channel are 0.048 mm
2
and
from 1.2 V supply voltage, respectively. The measured results show that the gain mismatch among channels is 0.8%, and the equivalent input impedance is 1.29
. Within 130 ms, DCDSL can calibrate a DC offset voltage of ±300 mV. The input-referred noise over the range of 0.1~100 Hz is
Vrms.
In this brief, a low power pipeline-parallel phase accumulator (PPA) with 32-bit frequency resolution and 10-bit phase resolution is proposed for direct digital frequency synthesizer (DDFS) applications. The proposed PPA is derived using the conventional pipeline and parallel phase accumulator (PA) architectures. To assess the performance of the proposed PPA, it is compared against the existing PAs in terms of design metrics (DMs) such as power, area, and a maximum frequency of operation. For a fair comparison, the PPA and existing PAs have been described using Verilog register-transfer-level (RTL) codes and synthesized under common constraints, using TSMC typical 180 nm standard cell library. The constraints used are the input delay = 250 ns, output delay = 250 ns, supply voltage Vdd = 1.8 V, and clock frequency (fclk) = 100 MHz. Cadence’s RC tool-based synthesis results show that the proposed PPA has a total power PT = 791.35 nW, area = 9307.26 μm2, and fmax=890 MHz. The proposed PPA saves 16.83% of total power and 3.31% of total area against the reported pipeline-parallel PA.
This paper presents seven novel ‘Lower-part approximate multi-bit adders’ (LAMAs). The LAMAs namely lower-part NOR, AND, NAND, XOR, XNOR, ‘lower-part constant-1 adder’ (LCONE), and ‘lower-part constant-0 adder’ (LCZERO) are derived based on the hardware architecture of ‘Lower-part OR adder’ (LOA). The performance metrics of these proposed adders are compared with LOA, lower-part NOT1, and lower-part NOT2. For a fair comparison an 8-bit LAMA is designed using Verilog ‘hardware-description-langauge’ (HDL). The 8-bit LAMA is divided into two equal segments namely ‘most-significant-bit’ (MSB) and ‘least-significant-bit’ (LSB) adders. The MSB adder is designed using ‘ripple carry adder’ (RCA) and LSB adder is designed using LAMA. To assess the performance of the proposed adders, all the ten adders are compared in terms of ‘design metrics’(DMs) such as power, delay, ‘power-delay-product’ (PDP), and area. To extract the DMs for performance comparison, all the ten adders have been designed using a Verilog ‘register-transfer-level’ (RTL) code. The RTL coded adders are then synthesized using Cadences’ ‘RTL-Compiler’(RC) tool, using 180 nm standard cell library. The synthesis results show that proposed LAMAs have better DMs compared to conventional LOA. Further to demonstrate the application of LAMAs, an image addition is performed using standard test images and their respective ‘peak-signal-to-noise-ratio’(PSNR) and ‘structural similarity index’ (SSIM) have also been extracted. The PSNR values of the proposed LAMAs are found to be better than the reported LAMAs.
Wireless implantable medical devices (IMDs) offer immense possibilities in health care. Since IMDs survive on battery energy, they suffer from serious power constraints. While studying the power concerns of IMDs, it is depicted that voltage-controlled oscillator (VCO) is a fundamental component in the transceiver which consumes significant energy compared to other elements. The quality of performance offered by voltage-controlled oscillator (VCO) in turn depends on the characteristics of constituent current mirror circuit section. In this work, an extensive comparison of performance of VCO is carried out for different current mirror designs to ensure the high standards of quality at power supply as low as 1.8 V. All the circuits have been implemented using spice at 0.032 µm TSMC CMOS.
Low-power is a paramount concern in the design of ‘digital signal processor’ (DSP) for the next generation portable electronic gadgets. The quest to achieve low-power with required speed has made the researchers look into various low-power circuit design techniques. In more recent years, reversible logic (RL) has emerged as an alternative and promising technique in the design of low-power DSPs for multimedia applications. The RL finds vast applications in the fields of nanotechnology, low-power CMOS circuit design, approximate computing, optical computing, and quantum computing, etc. The full adder (FA) being a primitive element of DSP plays a significant role in the contribution of the overall power of the system under consideration. This paper presents the design and comparison of state-of-the-art 1-bit FA architectures (FAAs) using standard reversible logic gates (RLGs). The designed FAAs herein referred to as ‘Reversible-logic based FAs’ (RFAs). The functionality of RFAs has been verified through Verilog HDL based simulations using Cadence’s NC simulator. The quantum merits of each RFA have also been assessed through the quantum gate metrics (QGMs).
Link to view paper:
https://rdcu.be/cuoGk
This paper proposes a Bio-signal instrumentation amplifier (Bio-IA) with fast recovery and constant bandwidth for wearable Bio-sensors. To shorten the offset calibration time of the Bio-IA and reduce the loss of Bio-signal in the calibration process, a digital-controlled DC servo loop (DCDSL) with fast recovery is designed, which achieves a larger offset calibration range and a faster calibration speed. The proposed programmable gain amplifier (PGA) with constant bandwidth uses dual-biased pseudo-resistor (PR) to stabilize the passband width under different gains, effectively preventing the loss of low-frequency signals. Besides, this paper analyzes the noise of the DCDSL and the noise of dual-biased PR for the first time. The presented Bio-IA was implemented in a 0.18-μm CMOS process, occupying a core area of 849 μm× 451 μm. The measured results show that the Bio-IA can calibrate a DC offset of ±511 mV, and the response time is less than 70 ms when the offset polarity changes suddenly. When the gain of the bio-IA varies from 26 to 40 dB, its passband width remains constant, and the high-pass and low-pass cut-off frequencies are 0.4 Hz and 200 Hz, respectively. The input-referred noise over the range of 0.1-200 Hz is 0.72 μVrms. The proposed Bio-IA consumes 5.5 μW from 1.2 V supply voltage.
Single event transients (SETs) have become increasingly problematic for modern CMOS circuits due to the continuous scaling of feature sizes and higher operating frequencies. Especially when involving safety-critical or radiation-exposed applications, the circuits must be designed using hardening techniques. In this brief, we present a new radiation-hardened-by-design full-adder cell on 45-nm technology. The proposed design is hardened against transient errors by selective duplication of sensitive transistors based on a comprehensive radiation-sensitivity analysis. Experimental results show a 62% reduction in the SET sensitivity of the proposed design with respect to the unhardened one. Moreover, the proposed hardening technique leads to improvement in performance and power overhead and zero area overhead with respect to the state-of-the-art techniques applied to the unhardened full-adder cell.
Current mirrors are fundamental to every analog block. This work proposes a novel design of low voltage, low power, and improved performance current mirror. The proposed current mirror circuit has negative and positive feedback paths to obtain maximal output resistance at 12 μA input current. Its performance is validated @ 90 nm technology at 0.75 V supply voltage. The bandwidth of the proposed Current mirror design is 748.847 MHz, and the minimum supply voltage is 0.045 V. Moreover, a remarkably high output resistance of 250 GΩ accomplished, it is the maximum value attained as compared to CMOS based state-of-art designs. The proposed design consumes 19.436 μW power, and the current transfer value is 0.016.
In today’s enhanced technological advancements, a carry select adder performs an indispensable integral part of the complex processing of data. It exhibits promising results in minimizing cost and power consumption. The logic operation of it has simulated over 90 nm CMOS technology of spice tool at 0.8 V. These works present a Carry select adder using multiplier and adder circuits. In proposed designs, extra circuitry is eliminated and leads to a reduction in 43.995% of power consumption, 93.912% of time delay, and 97.515% of energy. The transistor count of the proposed carry select adder is 61.788% less than that of the conventional carry select adder. The power, delay, energy of it has been compared with state-of-art carry select adder. This advanced circuit of adder shows highly efficient and reliable performance.
Bio-signal instrumentation amplifier (Bio-IA) is one of the most important circuit in the vital sign monitoring system. However, the performance of the Bio-IA using traditional pseudoresistor (PR) is always very sensitive to process, power voltage and temperature (PVT). This brief proposed a digitally controlled dc-servo loop (DCDSL) and an improved PR to improve the robustness of Bio-IA. The proposed DCDSL replaces the integrator-based DSL and eliminates the PR in the traditional DSL, which can improve the response speed as well as the noise performance. The presented Bio-IA was implemented in a standard 0.18 μm CMOS process, occupying an active area of 0.474 × 0.424 mm
2
. The measured results shows that the Bio-IA can operate in the temperature range of -20°C~80°C. When the bias current is 500 fA, the equivalent resistance of the improved PR can be up to 330 GQ. The proposed Bio-IA can calibrate the dc offset as large as ±300 mV with a response time less than 200 ms. When the dc offset increases from 0 to 300 mV, its input-referred noise varies from 0.67 μVrms to 1.49 μVrms. With 1.2 V supply voltage, the midband gain of the Bio-IA is 40 dB.
This work intends to prove that complex ternary combinational circuits can be custom designed using the conventional CMOS technology. This work focuses on implementing specific combinational circuits i.e. ternary 3 to 1 multiplexer circuit and Ternary Half Adder circuit in the conventional CMOS technology. In the binary digital system, it is known that any combinational logic can be implemented using multiplexer and basic logic gates. The same approach holds good in ternary logic as well. As almost any ternary combinational logic can be implemented using a ternary multiplexer, In this work it is proposed to design a fully customised ternary multiplexer. The proposed 3:1 ternary multiplexer will be used to design a ternary combinational circuit namely a Ternary Half Adder. As the aim of the work is to prove the feasibility of a ternary logic design on CMOS technology, the major attention is paid on realising the functionality of the ternary combinational circuits, rather than optimizing them for power. The circuits are designed and simulated in Cadence Virtuoso using 180 nm technology.
Residue number system (RNS) in computer arithmetic is an efficient parallel computation number system that employs forward conversion, residue arithmetic based arithmetic manipulation and reverses conversion, which all together increases the speed of computation in various digital signal processing applications. Nevertheless power requirement for the wireless sensor node is more important, hence this work focuses on the design and implementation of power efficient RNS based digital signal processor architecture using folded tree based parallel prefix adder by employing Chinese Remainder Theorem—I.
Employing cost-efficient, high-speed and fault-tolerant processing units is an essential goal in the design of current processors. In this paper, the carry select adder (CSeA) as one of the fastest adders is augmented respecting multiple-fault detection, delay, power and required area. In this way, based on the concept of a self-checking full adder, an m-bit logic-optimized self-checking single-stage CSeA is designed in which at most m concurrent faults can be detected. Then, based on a delay analysis, a new grouping structure for the self-checking multi-stage CSeA apart from the conventional square-root (SQRT) grouping is proposed to optimize the overall delay for different adder sizes. The proposed grouping structure decreases the power overhead, as well. Experimental results show that as well as an acceptable multiple-fault detection capability, noticeable improvements are achieved in delay and power consumption compared to the previous self-checking CSeA designs. The proposed CSeA reaches in average 20% power reduction and 34% speed improvement in different sizes compared to the best existing design.
This paper presents a high-speed, energy efficient carry select adder (CSLA) dominated by carry generation logics. The proposed architecture is composed of three functional stages – a Primary Carry Unit (PCU), an Intermediate Wave Carry Unit (WCU) and a Final Selection Unit (FSU) – that are partitioned with the appropriate bit-width. We synthesized the blocks with random logic use functional blocks for which the input and output consist only of carry functions. The CSLA is partitioned into bit-slice logics to reduce the propagation delay, and we analytically optimized the bit-slice width of the functional blocks. The proposed architecture skips the carry computation in the first stage of each bit-slice block. We used 180 nm CMOS technology to implement the proposed CSLA for various input bit widths. The results show that the proposed CSLA reduces the computational delay by 24%, power consumption by 17% and PDP by 37% compared to conventional implementations.
A body bias technique for low power full adder using XOR gate and pseudo NMOS transistor
- P Malik
- M Kumar
- M Zunairah
Design and implementation of ripple carry adder using various CMOS full adder circuits in 180nm and 130nm technology
- V Haribabu
- C Malasri
- O Jyothirmai
- T Pranathi