From Wide to Ultrawide-Bandgap Semiconductors for High Power and High Frequency Electronic Devices

Abstract

Wide and ultrawide-bandgap (U/WBG) materials have garnered significant attention within the semiconductor device community due to their potential to enhance device performance through their substantial bandgap properties. These exceptional material characteristics can enable more robust and efficient devices, particularly in scenarios involving high power, high frequency, and extreme environmental conditions. Despite the promising outlook, the physics of UWBG materials remains inadequately understood, leading to a notable gap between theoretical predictions and experimental device behavior. To address this knowledge gap and pinpoint areas where further research can have the most significant impact, this review provides an overview of the progress and limitations in U/WBG materials. The review commences by discussing Gallium Nitride, a more mature WBG material that serves as a foundation for establishing fundamental concepts and addressing associated challenges. Subsequently, the focus shifts to the examination of various UWBG materials, including AlGaN/AlN, Diamond, and Ga2O3. For each of these materials, the review delves into their unique properties, growth methods, and current state-of-the-art devices, with a primary emphasis on their applications in power and radio-frequency electronics.

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J. Phys. Mater. 7(2024) 022003 https://doi.org/10.1088/2515-7639/ad218b
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TOPICAL REVIEW
From wide to ultrawide-bandgap semiconductors for high power
and high frequency electronic devices
Kelly Woo1,3, Zhengliang Bian1,2,3, Maliha Noshin1,3, Rafael Perez Martinez1,
Mohamadali Malakoutian1, Bhawani Shankar1and Srabanti Chowdhury1,∗
1Department of Electrical Engineering, Stanford University, Stanford, CA, 94305, United States of America
2Department of Mechanical Engineering, Stanford University, Stanford, CA, 94305, United States of America
3These authors contributed equally to this work as co-first authors.
∗Author to whom any correspondence should be addressed.
E-mail: srabanti@stanford.edu
Keywords: ultrawide-bandgap, power electronics, radio-frequency devices, gallium nitride, aluminum nitride, diamond, gallium oxide
Abstract
Wide and ultrawide-bandgap (U/WBG) materials have garnered significant attention within the
semiconductor device community due to their potential to enhance device performance through
their substantial bandgap properties. These exceptional material characteristics can enable more
robust and efficient devices, particularly in scenarios involving high power, high frequency, and
extreme environmental conditions. Despite the promising outlook, the physics of UWBG materials
remains inadequately understood, leading to a notable gap between theoretical predictions and
experimental device behavior. To address this knowledge gap and pinpoint areas where further
research can have the most significant impact, this review provides an overview of the progress and
limitations in U/WBG materials. The review commences by discussing Gallium Nitride, a more
mature WBG material that serves as a foundation for establishing fundamental concepts and
addressing associated challenges. Subsequently, the focus shifts to the examination of various
UWBG materials, including AlGaN/AlN, Diamond, and Ga2O3. For each of these materials, the
review delves into their unique properties, growth methods, and current state-of-the-art devices,
with a primary emphasis on their applications in power and radio-frequency electronics.
1. Introduction
Wide bandgap (WBG) materials, such as Silicon Carbide (SiC) and Gallium Nitride (GaN), have
unequivocally demonstrated their versatility across various fields, including optics, power electronics, and
radio frequency (RF) technology. This has led to a significant expansion of their applications and a
burgeoning market presence. What sets them apart is their exceptional ability to operate effectively in
high-temperature and challenging environments. The progress in WBG materials is now driving substantial
interest in an emerging class of semiconductors known as ultrawide-bandgap (UWBG) materials,
distinguished by even wider bandgaps. Both WBG and UWBG materials exhibit remarkable resistance to
electric field breakdown due to their large bandgap, offering a multitude of advantages to electronic devices
and systems. These benefits encompass enhanced efficiency, the capability for high-temperature operation,
smaller footprints, simplified system designs, and reduced overall system costs. Ultimately, broader positive
impacts such as diminished carbon emissions and closure of the digital divide can result from the successful
development of these technologies. In terms of specific device applications, today GaN has asserted its
dominance in lighting technology, with noteworthy contributions in radar and telecommunication as well.
Additionally, GaN has made significant inroads into power electronics. SiC, on the other hand, has excelled
in medium to high-power electronics and serves as an excellent substrate for GaN RF technology.
Consequently, there exists both a symbiotic and competitive relationship between SiC and GaN, shaping the
current landscape of applications and markets. Their collective successes have firmly established WBG
materials on the technological map, paving the way for the exploration of UWBG materials.
© 2024 The Author(s). Published by IOP Publishing Ltd

J. Phys. Mater. 7(2024) 022003 K Woo et al
Table 1. Material properties of GaN and emerging UWBG semiconductors and their Baliga and Johnson figure of merits [3,4]
(references therein).
Material Parameters GaN β-Ga2O3Diamond AIN
Bandgap Eg(eV) 3.4 4.8 5.5 6.0
Critical Field Ecr (MV cm−1) 3–3.5 8–10.3 10–13 15.4
Electron mobility µe(cm2V−1s−1) 1000 180 4500 426
Hole mobility µh(cm2V−1s−1) 24 — 3800 —
Relative permittivity εr10.4 10 5.7 9.76
Electron saturation velocity vsat (107cm s−1) 1.5–2.0 1.1 2.3 1.3
Thermal conductivity K(W m−1K−1) 253 11–27 2290–3450 285–319
Baliga FOM (106V2Ω−1cm−2) 27 900 36 300 554 000 336 000
Johnson FOM (1012 V s−1) 11 18 29–47 31.9
Figure 1. (a) Material properties of U/WBG semiconductors presented in a spider chart; (b) the theoretical BFOM of these
materials compared to Si.
The significance of semiconductor technology and its sustainability are frequently assessed through its
market size. In the power semiconductor sector, the projected global market for Silicon Carbide is $6 billion,
and for Gallium Nitride $2 billion by the year 2027 [1]. This substantial growth can be predominantly
attributed to the expansion of hybrid and electric vehicles and several other key sectors, including, power
supplies, military/aerospace applications, as well as renewable energy and smart grids. In the GaN RF
market, an annual revenue of $1.8 billion in 2022 is predicted to increase to $2.7 billion by 2028 [2]. This
significant commercial revenue stems from the utilization of high electron mobility transistors (HEMTs) for
power amplifiers in wireless base stations. Furthermore, the increased efficiency and reliability offered by
RF-oriented GaN find valuable applications in radar systems within the defense sector.
UWBG materials, like AlGaN/AlN, diamond, and β-Ga2O3, have similar applications to those of WBG
materials; however, with significantly larger bandgaps than 3 eV, they promise to offer even higher
performance metrics. The electronic properties of GaN and UWBG materials are listed in table 1and
illustrated in figure 1. A simple method to quantify a device’s suitability for power applications (specifically
low frequency unipolar power switching) is by the Baliga figure of merit (BFOM): Vbr2/Ron,sp or 1
4εµEcr3,
where Vbr is the breakdown voltage, Ron,sp is the specific on-resistance, εis the dielectric constant, µis the
carrier mobility, and Ecr is the critical electric field. A higher value indicates that a device can sustain high
blocking voltages while incurring minimal on-state losses, which can be visualized in figure 1(b). Thus, the
critical electric field, which typically scales with the bandgap has a large influence on the BFOM. For high
frequency power applications, the Johnson figure of merit (JFOM) is used: vsatEcr/2π, where vsat is the
saturation velocity. According to both FOMs, UWBG materials provide significant improvement in
comparison to GaN which itself greatly surpasses Si in high power and frequency device performance.
In this comprehensive review article, our primary focus is on the exploration of electronic device
technology led by GaN as a well-established technology, along with emerging technologies such as
AlGaN/AlN, Diamond, and β-Ga2O3. Our discussion will revolve around various aspects of these materials
of interest, including their material properties, growth techniques, devices, and applications, providing an
ample overview of their significance in the field of electronic device technology. While we recognize the
significance of Silicon Carbide, it is not included in this article, and we would like to direct interested readers
to some outstanding recent reviews on this subject [5,6].
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J. Phys. Mater. 7(2024) 022003 K Woo et al
Figure 2. (a) Image of 2 inch. c-plane ammonothermal-GaN substrate (manufactured at AMMONO company) [20]; (b) 6 inch
GaN crystal grown on MOCVD-GaN seeds using Na-flux method [21]; (c) 2 inch HVPE-GaN wafer with a thickness of 500 µm
and an etch pit density of 5 ×104cm−2[22].
2. Gallium nitride (GaN)
2.1. Material properties
The electron mobility in bulk GaN at room temperature is dependent on the doping, where it can reach
1000 cm2(V·s)−1at low doping concentrations of 1015–1016 cm−3and decreases to 200–600 cm2(V·s)−1in
the doping range of 1017–1018 cm−3. The hole mobility is much lower, typically less than 100 cm2(V·s)−1,
and drops to around 10–30 cm2(V·s)−1in the doping range of 1017–1018 cm−3. A detailed mobility model
for GaN describing the doping and temperature dependence is well documented [7]. On the other hand, the
electron mobility in the two-dimensional electron gas (2DEG) formed at the AlGaN/GaN interface can reach
up to 2000 cm2(V·s)−1at room temperature [8], motivating the development of GaN-based HEMTs. For
high-field transport, the highest electron saturation velocity in GaN was reported to be 2–2.5 ×107cm s−1
[9,10], while the hole saturation velocity was limited to 0.7 ×107cm s−1[11,12].
The intrinsic breakdown in a material is caused by avalanche initiated by the impact ionization at high
electric fields. A critical field of 3–3.5 MV cm−1is estimated for GaN by the empirical formula in terms of its
3.4 eV bandgap [4]. In recent years, avalanche has been routinely achieved in GaN PN structures with proper
doping profiles and efficient field management designs due to the availability of higher-quality native GaN
substrates. Several photo-multiplication-based methods have been utilized in experiments to extract the
impact ionization coefficients for electrons and holes in GaN [13–15]. Based on these coefficients, a
physics-based model describing the critical field regarding doping concentration in GaN has been proposed
[16].
For high power and frequency devices, the thermal properties of the materials become increasingly
important as self-heating becomes a larger issue. The thermal conductivity (TC) of a material dictates how
efficiently it can dissipate heat. For GaN, the TC is moderately high, around 170–220 W (m·K)−1[17,18],
and was reported to be sensitive to the doping concentration and dislocation density.
2.2. Growth and doping
2.2.1. Bulk substrate growth
The past few decades have witnessed the rapid development of GaN-based electronic devices from
experimental prototypes to successful commercialization. The scalability and quality of native GaN
substrates play a critical role in reducing the manufacturing costs of GaN to further boost its commercial
appeal, however, they still require more research efforts within the nitride community. The decomposition
pressure at the melting point for GaN is around 6 GPa [19], leading to intrinsic difficulties in adopting the
traditional melt growth method for bulk GaN substrates. Numerous research efforts in developing new
crystal growth technology for GaN have been made, mainly consisting of three growth methods:
ammonothermal growth, sodium-flux (Na-flux) growth, and hydride vapor phase epitaxy (HVPE). Figure 2
shows the images of the bulk GaN substrates grown by each of these methods.
The ammonothermal method begins by solubilizing polycrystalline (PC) GaN feedstock in supercritical
ammonia under high pressure (100–500 MPa) [23,24]. Then, the dissolved materials are transported to the
recrystallization region along a temperature gradient and growth on the seeding crystals occurs at
temperatures of 500 ◦C–600 ◦C [23,25,26]. 2 inch GaN bulk substrates with a dislocation density down to
5×103cm−2were successfully demonstrated with the ammonothermal growth method [20]. The method’s
primary limitation is its relatively slow growth rate of around a few micrometers per hour.
Na-flux growth also belongs to the category of solution growth approaches but produces a more
favorable growth condition by using sodium flux. The typical temperature and pressure during growth are
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around 750 ◦C–900 ◦C and 5 MPa [27–30], respectively. Today, this method can produce a 6 inch
crystallographically flat GaN wafer with high structural quality [31], and the typical dislocation density of
the Na-flux method is around 104–106cm−2[32].
Finally, the knowledge of HVPE growth of GaN was appropriated from the growth of GaAs and InP. In
this method, chloride gas reacts with a gallium source and forms a gaseous phase in the source zone
(800 ◦C–900 ◦C). The product is then transported to the nitrogen source in the deposition zone
(1000 ◦C–1100 ◦C) for further reaction and crystallized as GaN [22,33]. The most significant advantages of
HVPE growth include the atmospheric pressure condition and a high growth rate on the order of several
hundreds of micrometers per hour [34]. However, the size and thickness of the wafer are limited by the
bowing of the crystallographic planes due to the lattice mismatch between GaN and the seeding materials.
2.2.2. Epitaxial layer growth
Several epitaxial growth methods have been developed for GaN thin-film growth on either native or
nonnative substrates, including HVPE [35–38], molecular beam epitaxy (MBE) [39–42], and metalorganic
chemical vapor deposition (MOCVD) [43–45]. When growing on nonnative substrates, a low-temperature
AlN buffer layer is usually adopted to improve the surface morphology and increase the crystal quality by
mitigating the lattice mismatch between GaN and foreign substrates [46]. Homoepitaxial growth on native
GaN substrates does not require such a buffer layer. MBE growth provides precise control of the impurity
and thickness of the film during the growth; however, it usually requires a high-vacuum atmosphere.
MOCVD is considered to be the leading technique for the growth of III–V-nitride materials for mass
production [47]. The use of high-purity chemical sources, characteristic of this method, yields a high degree
of composition control and uniformity, high growth rates, and large-scale manufacturing potential.
2.2.3. Doping
Si is the most commonly used dopant element for donors in GaN by substituting the Ga sites [48]. The Si
doping concentration can be well controlled by adjusting the flow rate of the gaseous source, for example,
SiH4or Si2H6, over the range from 1016 to 1019 cm−3without forming cracks and surface pits during growth
[49,50]. It was demonstrated that Si offered shallow donor states (around 10–20 meV) in GaN [51,52],
giving rise to a nearly complete ionization ratio at room temperatures. Furthermore, nitrogen vacancies in
GaN can also provide unintentional n-type doping in GaN [53,54].
P-type doping in GaN was also successfully achieved by using Mg as acceptors, which led to the invention
of the blue LED utilizing a GaN PN junction. However, Mg-doped GaN tends to be electrically insulating if
grown in the presence of hydrogen. The role of H atoms in passivating the Mg acceptors in GaN was
elucidated as the H atoms were found to form neutral Mg–H complexes [55,56]. The Mg–H bonds can be
broken by low-energy electron beam irradiation or a high temperature thermal anneal above 700 ◦C [55,57],
which gives free holes in GaN. Due to the relatively high activation energy of Mg (130–180 meV reported) in
GaN [58–60], the ionization ratio of Mg acceptors is typically less than 10%. Achieving a high hole
concentration and high p-type conductivity with Mg remains critical for the GaN community.
Given the material properties and growth techniques summarized in the previous sections, we will
discuss a few fundamental device structures and their applications to elucidate the importance of GaN in
power and radio-frequency electronics.
2.3. GaN devices and applications
2.3.1. High power devices
2.3.1.1. Schottky barrier diodes (SBDs)
The SBD is one of the basic rectifiers used in power electronics. Due to its majority carrier transport
mechanism, it has the advantage of low turn-on voltage, fast switching, and thus low switching losses.
However, the thermionic field emission transport at the metal–semiconductor interface leads to a rapid
increase of leakage current at high surface electric fields, limiting the breakdown performance of GaN SBDs.
Thus, from a device engineering perspective, efficient edge termination designs are needed to relax the field
concentration at the anode edge to improve the breakdown.
Almost all reported GaN SBDs are based on an n-type drift region due to the excellent controllability of
n-type GaN growth. Nickle (Ni) is one of the most commonly used contact metals for GaN. GaN SBDs can
be simply fabricated by depositing a Schottky contact after the epitaxial growth of the drift region. In this
configuration, the field concentration at the anode edge leads to a premature breakdown. The field plate
structure (figure 3(a)) is an effective method to mitigate the peak electric field at the edge of the anode, thus
enhancing the breakdown voltage [61,62]. A GaN SBD over 1 kV was reported in 2010 by using a field plate
on SiNxlayers for edge termination. Furthermore, growth optimization yielded a structure with a high bulk
electron mobility of 930 cm2(V·s)−1, which contributed to a low specific on-resistance of 0.71 mΩ·cm2[61].
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Figure 3. Schematics of different edge terminations in GaN SBDs: (a) GaN SBD with field plate (FP); (b) GaN SBD with ion
implantation termination; (c) GaN SBD with trench metal–insulator–semiconductor configuration.
As shown in figure 3(b), the implantation of several species, such as Argon (Ar) and Fluorine (F), was
reported to successfully convert n-type GaN to a highly-resistive region [63–66]. This high-resistivity region
helps spread the potential along the surface, resulting in a mitigated electric field at the edge and reduced
leakage current. Utilizing this technique, a 1.7 kV GaN SBD with Ar implantation termination has been
achieved [64], and F implantation also showed a boost of breakdown voltage from 155 V to 775 V in GaN
SBDs [67]. Similarly, plasma nitridation can increase the energy barrier height at the edge by compensating
the nitrogen vacancies [68], offering a superior breakdown voltage of 995 V compared to 335 V without
nitridation termination [69].
Trench metal–insulator–semiconductor barrier Schottky diodes (TMBS) have been proposed to
effectively modulate the surface electric field at the Schottky contact to achieve a more uniform field
distribution [70–72]. A representative TMBS structure is shown in figure 3(c). However, the peak field at the
trench corner may also lead to field crowding and premature failure in the dielectrics. Thus, Zhang et al
reported a novel TMBS structure with Ar implantation beneath the trench oxide, which mitigated this issue
[73]. This method effectively enhanced the breakdown voltage from 500 V to 700 V after implantation
treatment without degrading the forward characteristics.
2.3.1.2. PN junction diodes (PNDs)
GaN PNDs show lower leakage current and better thermal stability compared to GaN SBD diodes, despite
their relatively high turn-on voltage. In contrast to SBDs, the peak electric field in PNDs appears near the
junction instead of at the metal contacts as in GaN SBDs. Thus, the peak electric field can be buried inside
the bulk, which prevents premature breakdown and improves the feasibility of achieving avalanche in vertical
GaN PN diodes. Thanks to the increasing availability of native bulk GaN substrates with low dislocation
density, the avalanche phenomenon has been more routinely reported in GaN PN structures. While
avalanche is recognized as a performance benchmark in power devices, the off-state leakage current is
another important metric in determining the power loss. The relationship between dislocation density and
leakage current under the prerequisite of avalanche has been experimentally examined [74]. It was suggested
that Poole–Frenkel effects dominated when the dislocation density was in the range of 104cm−2and
variable-range-hopping mechanisms dominated when a higher dislocation density (106cm−2) was present
in the device.
In GaN PND fabrication, mesa etches are the most versatile edge termination method used. Several edge
terminations based on mesa etch are shown in figures 4(a)–(d). The deep mesa etch of the entire drift region
creates a uniform electric field distribution, almost the same as in a 1D ideal planar structure [75].
Combined with a sidewall passivation layer, a deep mesa-etched diode was able to produce an 880 V
avalanche in a GaN PN diode. A small-angle bevel mesa was also reported to effectively modulate the electric
field near the PN junction [76,77]. However, the bevel design is very sensitive to the ratio of the doping
concentration and the bevel degree [78]. Field plating on a beveled mesa further mitigates the peak electric
field near the junction, showing great potential in high-voltage kV-class GaN PND with avalanche capability
[79,80]. A 3.48 kV breakdown voltage and low specific on-resistance of 0.95 mΩ·cm2have been achieved
using field plating in a GaN PN structure [80]. Recently, a junction termination extension (JTE) based on
multiple-step mesa etched was successfully demonstrated in vertical GaN PN diode, resulting in an avalanche
breakdown voltage of over 6 kV in GaN [81,82]. Mg implantation into the sidewall after a mesa etch
demonstrated a 1.5 kV avalanche in vertical GaN PNDs [83] without the need for an anneal to activate Mg.
Instead, the implanted positive species create a depletion layer underneath the sidewall, shielding the high
electric field at the surface, thus reducing the surface leakage.
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J. Phys. Mater. 7(2024) 022003 K Woo et al
Figure 4. Schematics of different edge terminations adopted in GaN PNDs leading to avalanche breakdown: (a) GaN PND with
deep mesa etch; (b) GaN PND with bevel angle mesa etch; (c) GaN PND with field plate on top of a beveled mesa; (d) GaN PND
with junction termination extension (JTE) based on multiple-step mesa etch; (e) GaN PND with ion implantation compensation;
(e) GaN PND with field plate on top of passivated p-GaN by hydrogen plasma treatment.
Nitrogen ion implantation compensation offers a planar edge termination without the requirement of a
mesa etch (figure 4(e)). The partially compensated p-GaN layer helps to laterally distribute the electric field
to support a high voltage [84,85]. A SiNxsurface passivation layer is required to suppress the surface leakage.
Contrary to the activation process of an Mg-doped p-GaN layer, hydrogen plasma treatment was
demonstrated to passivate the Mg in p-GaN again by forming neutral Mg–H complexes, creating a
high-resistivity layer [86–88]. Hydrogen plasma based guard ring structures showed a vertical GaN PND
with 1.7 kV breakdown and 0.65 mΩ·cm2specific on-resistance [89]. Adding a field plate on the passivated
p-type layer helped reduce the electric field around the corner of the junction (figure 4(f)), resulting in a
2.8 kV avalanche breakdown device, justifying the application of hydrogen plasma treatment in fabricating
high-voltage GaN PNDs [90].
2.3.1.3. Junction barrier diodes and superjunctions
Junction barrier diodes (JBS) incorporate the merit of low turn-on voltage and reduced leakage current from
an SBD and PND design. GaN JBS diodes fabricated by Mg ion implantation followed by a multi-cycle rapid
thermal annealing (RTA) method exhibited a >600 V breakdown voltage but a very large specific
on-resistance >100 mΩ·cm2[91]. Later, multiple pulsed thermal annealing at 1350 ◦C was reported to
partially recover the implantation damage and activate the implanted Mg, leading to an improved specific
on-resistance of 1.7 mΩ·cm2with a 600 V breakdown [92]. Matys et al obtained the high activation ratio of
implanted Mg by implementing the thermal annealing under ultra-high pressure at 500 MPa, leading to a
high-quality p-type JTE structure, offering a nondestructive breakdown voltage of 675 V with a low
on-resistance of 0.67 mΩ·cm2[93]. Recently, Zhou et al also demonstrated the avalanche capability in
Mg-implanted GaN JBS [94].
A superjunction structure (SJ) theoretically gives rise to a better trade-off relationship between
breakdown voltage and the specific on-resistance since the charge balancing does not require lowering the
doping concentration in the drift region to achieve a high-voltage blocking. However, due to the difficulties
in achieving a deep column of p-type GaN, vertical SJs in GaN are rarely reported. Xiao et al demonstrated a
heterogeneous GaN SJ by using p-type NiO as a p-type column filling [95]. The schematics of the fabricated
device and SEM cross-section images are shown in figures 5(a) and (b). The forward characteristics of the
device exhibited two stages of turn-on behavior, corresponding to NiO/GaN and GaN PN junction,
respectively. The fabricated SJ offered a 1.1 kV breakdown voltage with an on-resistance of 0.15 mΩ·cm2,
exceeding the unipolar GaN limit. The leakage current was attributed to the sidewall interface of GaN/NiO
and avalanche was not observed. With the development of Mg ion implantation technology in GaN,
increasing reports of homogeneous GaN SJs can be expected.
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J. Phys. Mater. 7(2024) 022003 K Woo et al
Figure 5. (a) Schematic of the vertical GaN superjunction diode and the zoom-in of a SJ unit-cell; (b) cross-section FIB-SEM
images of the SJ region of the fabricated SJ-PNDs; (c) forward I–V characteristics of GaN SJ-PNDs plotted; (d) reverse I–V
characteristics of the GaN-on-GaN SJ-PNDs with different spacings [95].
2.3.1.4. HEMTs for power electronics
A 2DEG can be generated at an AlGaN/GaN interface without any intentional doping due to the
polarization-induced charges [96,97]. High electron mobilities up to 2000 cm2(V·s)−1at room temperature
and high sheet carrier densities of 1013 cm−2can be obtained in the 2DEG channel [8]. Low-resistance
transistors based on the 2DEG channels in the AlGaN/GaN heterostructures are referred to as HEMTs. The
GaN HEMT has been one of the most successfully commercialized devices in the GaN family. In 2014–2015,
Transphorm Inc. first announced their cascode packaged 600 V GaN HEMTs as power switches which meet
the standards of the Joint Electron Devices Engineering Council (JEDEC), marking a milestone in the
commercialization of GaN in system products [98,99].
Typically, GaN HEMTs adopt a lateral configuration, consisting of several epitaxial layers on foreign
substrates, such as Si, Sapphire, or SiC. The mismatch of the lattice constants and coefficients of thermal
expansion between GaN and the foreign substrates usually leads to a high dislocation density
(108–1010 cm−2) [100–102], which can be a major source of leakage current and degrade the electrical
properties of the 2DEG. Thus, an AlN nucleation layer is typically used as a starting layer for GaN growth to
mitigate the stress during the growth and cooling process [46,103,104]. On top of an AlN nucleation layer,
proper design and growth of buffer layers are critical for HEMTs. A step-graded AlGaN buffer, several
microns in thickness, or a GaN/AlN superlattice structure can be adopted to further mitigate the lattice
mismatch before growing the AlGaN/GaN channel [105,106], which helps to maintain the excellent
electrical properties of the 2DEG.
Due to the nature of the 2DEG channel, HEMTs are usually normally-on devices; however, normally-off
operation is preferred in most electronic applications. The cascode configuration, depicted in figure 6(a),
allows the normally-off operation of a GaN HEMT without changing the device structure by utilizing a
normally-off Si metal-oxide-semiconductor field-effect-transistor (MOSFET) in series with the GaN HEMT
device [107–109]. A monolithically integrated Si–GaN cascoded FET has been demonstrated, offering a
threshold voltage (Vth) of 3.2 V, a specific on-resistance of 3.3 mΩ·cm2, and a high breakdown voltage of
696 V [110]. However, the complexity of the packaging process and the limitation of high-temperature
operation by the Si devices remain challenges to be addressed [111].
The recessed gate structure (figure 6(b)) fabricated by etching the AlGaN barrier layer beneath the gate
followed by the deposition of a dielectric layer is another approach to achieve normally-off HEMTs
[112–114]. The thinning of the AlGaN layer beneath the gate selectively removes the 2DEG in that region
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J. Phys. Mater. 7(2024) 022003 K Woo et al
Figure 6. Schematic view of different architectures in achieving normally-off mode GaN HEMT: (a) cascode configuration in
series with a normally-off Si metal–oxide–semiconductor field-effect-transistor, with the effective gate (G), drain (D), and source
(S) depicted; (b) GaN HEMT with a recessed gate; (c) GaN HEMT with fluorine implantation under the gate; (d) GaN HEMT
with a p-GaN gate.
and shifts the threshold voltage. The etch process is critical, as the plasma-induced damage and the surface
roughness caused by etching can degrade the electrical properties of the 2DEG channel [115]. The choice of
the gate dielectric is also important for reducing surface states and gate leakage, thus improving the channel
mobility and the stability of the threshold voltage [116–119]. The integration of a slant field plate enabled an
enhancement mode GaN HEMT with a high breakdown voltage of 1.7 kV and a specific on-resistance of
3 mΩ·cm2[120]. Fluorine implantation (figure 6(c)) is another attractive method to offer a normally-off
operation without plasma etching [121,122]. The implanted negative fluorine ions change the surface
potential and deplete the 2DEG underneath. However, the hysteresis related to the charge trapping effect and
the stability of the fluorine ions in the AlGaN/GaN structure are still practical concerns for this method [123,
124].
Finally, the p-GaN/AlGaN gate (figure 6(d)) is an alternative promising technique to achieve a positive
threshold voltage [125–127]. The presence of a p-type layer elevates the band diagram in the AlGaN barrier
layer, resulting in the depletion of 2DEG at zero bias. A high Mg concentration is required for the desired
threshold voltage due to the low ionization ratio of Mg acceptors, however, the crystal quality of GaN may
deteriorate with a high Mg concentration [111]. Another feature of the p-GaN gate architecture is the
formation of a ‘p–i–n’ structure across the p-GaN gate, AlGaN barrier, and the GaN channel, which injects
additional holes and increases the current capabilities [128]. Additionally, the hole injections assist in
de-trapping the electrons captured at the surface states near the drain edge. This helps mitigate current
collapse in the device [129], a phenomenon in which the channel resistance increases and current decreases
when a high voltage is applied and diminishes the efficiency.
2.3.1.5. Vertical transistors
Despite the excellent conductivity offered by the high carrier density as well as high mobility in GaN HEMTs,
vertical configuration transistors are typically favored in power switch applications for higher current
density, voltage scalability, and better suppression of the peak electric field.
The vertical trench MOSFET (figure 7(a)) was reported first during the early stages of research due to its
relatively easy process in GaN technology. Normally-off operation and tuning of the threshold voltage are
possible in trench MOSFETs by adjusting the doping concentration of the p-type buried layer and by
choosing the gate dielectric material and thickness. Otake et al demonstrated a vertical V-shape trench
MOSFET, with a threshold voltage of 5.1 V [130]. In 2015, Oka et al reported a 1.2 kV-class trench MOSFET
with a specific on-resistance of 1.8 mΩ·cm2by using field plate edge termination in conjunction with a
hexagonal trench gate layout [131]. The low channel mobility arising from the etched semiconductor/gate
dielectric interfaces was shown to significantly degrade the on-state performance of the GaN trench
MOSFET. To address this issue, the GaN interlayer-based trench MOSFET (OG-FET), as shown in
figure 7(b), was proposed and prototyped by Gupta et al [132,133]. The OG-FET incorporated a thin
unintentionally doped (UID) GaN interlayer grown at the sidewall of the trench followed by an in-situ gate
dielectric deposition. The regrown channel offered higher mobility by reducing impurity and interface state
scattering. Ji et al reported an OG-FET with a channel mobility of 185 cm2(V·s)−1, resulting in an
on-resistance of 2.2 mΩ·cm2for a 1.4 kV transistor enabled by the double FP design [134]. Recently, Tanaka
et al demonstrated a 1.2 kV vertical GaN MOSFET based on an all-planar ion implantation process without
etch [135].
Unlike the trench MOSFET, a current aperture vertical electron transistor (CAVET), shown in figure 7(c)
takes advantage of the high mobility of a 2DEG, offering lower on-state resistances and higher current
capabilities [136,137]. CAVETs usually operate under normally-on conditions due to the existence of the
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J. Phys. Mater. 7(2024) 022003 K Woo et al
Figure 7. Schematic view of different architectures of vertical GaN transistors: (a) GaN trench MOSFET; (b) GaN interlayer-based
trench MOSFET (OG-FET); (c) GaN current aperture vertical electron transistor (CAVET); (d) GaN FinFET; (e) GaN junction
field-effect-transistor (JFET).
2DEG; however, normally-off devices can be achieved by adopting similar process techniques used for
HEMTs, as mentioned in section 2.3.1.4 [138,139]. In a CAVET, the current blocking layer is the key to
obtaining a high breakdown voltage [140]. An active buried p-GaN layer is ideal for this and allows for
avalanche capability; however, from a processing perspective, it is difficult to obtain due to the lack of a
mature ion implantation process. Therefore, regrowth of the channel in the aperture is usually required for
fabricating CAVETs. Shibata et al demonstrated a normally-off CAVET with a p-GaN gate, offering 1.7 kV
breakdown voltage and 1 mΩ·cm2specific on-resistance [141], consequently justifying this device design.
Carbon-doped semi-insulating GaN has also been studied as a current blocking and channel layer in vertical
GaN transistors [142]. A recent demonstration of a GaN vertical transistor with a semi-insulating channel
achieved an on–off ratio of 107and only marginal trapping effects under 200 ns pulsed mode operation
[143]. The growth and integration of a semi-insulating GaN layer may open alternative pathways in
designing novel device configurations for vertical GaN transistors.
More recently, transistors utilizing a fin structure (often referred to as GaN-FinFETs), shown in
figure 7(d) were prototyped [144–146]. Without the need for a p-type GaN layer, a sufficiently thin
fin-shaped channel can be well controlled simply by electrostatic modulation of the gate. For that reason,
normally-off operation can be achieved by narrowing the fin width and lowering the doping concentration
in the fin. The GaN FinFET exhibited excellent on-state performance due to high electron mobility in the
bulk GaN crystal. 1200 V class FinFETs have been demonstrated by Zhang et al with low on-resistance and
normally-off behavior; however, these devices suffered from catastrophic breakdown [145]. The junction
field-effect transistor (JFET), a subset of FinFETs in GaN is shown in figure 7(e). In this device, p-type GaN
is regrown surrounding the n-type fin channel and pinches off the channel by expanding the depletion
region of the PN junction. JFETs avoid the possible oxide reliability issues in an MOS structure, encouraging
avalanche in a three-terminal device. A 1.2 kV GaN JFET was reported by Liu et al using nitrogen
implantation termination [147]. This design exhibited robust avalanche capability up to 200 ◦C, showing
great potential in medium-voltage power applications [148].
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J. Phys. Mater. 7(2024) 022003 K Woo et al
2.3.2. RF devices
2.3.2.1. RF and mm-wave HEMTs
Due to its WBG, high electron mobility, and saturated electron velocity, GaN offers obvious advantages for
high-power and high-frequency transistors in terms of output power and efficiency [149]. The formation of
a 2DEG channel at the AlGaN/GaN interface, characterized by high sheet carrier density and high electron
mobility, leads to reduced channel resistances and enhanced current capabilities. This makes GaN superior to
SiC, particularly in high-frequency applications, even though both materials exhibit similar breakdown
properties. However, the absence of a process to grow bulk GaN hindered the development of GaN devices
and slowed down its technological maturation. GaN technology witnessed a resurgence of interest when the
first GaN LEDs were developed in 1993 by Nakamura et al [150] sparking a global competition for the
advancement of the field. The development of LEDs not only propelled the GaN market but also facilitated
breakthroughs in the RF domain, particularly with the introduction of the first microwave GaN power
HEMT in 1996 and the debut of the first GaN monolithic microwave integrated circuit (MMIC) occurring in
2000 [151].
Among the many challenges faced by GaN RF electronics, thermal management became of high
importance in high-power GaN monolithic MMICs as this issue hindered amplifier efficiency and reliability.
This concern was mitigated through the introduction of SiC semi-insulating substrates during the growth of
GaN HEMTs, boasting a TC that was seven times greater than that of GaAs, and ultimately enabled record
power densities exceeding 10 W mm−1[152]. Initial demonstration of GaN devices showcased a tenfold
improvement in output power density performance relative to Si laterally-diffused
metal–oxide–semiconductor (LDMOS) devices, which offered an output power density of 1 W mm−1[153].
Process innovation and novel device design to combat current collapse consume a large fraction of the
current research efforts in GaN HEMTs. The surface states on top of the AlGaN layer constitute the source of
the electrons in the 2DEG channel, however, trapping effects related to these surface states are believed to be
one of the major causes of current collapse (also referred to as dispersion) [154,155]. There are three major
technical routes to suppress this dispersion, which severely degrades the RF output power of GaN HEMTs.
The first approach is the introduction of a passivation layer. Employing SiNxwas demonstrated to effectively
reduce the surface states and led to a significant improvement of output power up to 11.2 W mm−1at
10 GHz [156,157]. Another method is the adoption of field plate technology [152,158], which enabled the
record output power of 41.4 W mm−1at 4 GHz and 30.6 W mm−1at 8 GHz in GaN HEMTs (figures 8(a)
and (b)) [159,160]. The double field plate not only mitigated dispersion effects but also helped in reducing
the peak electric field at the drain-side edge of the gate. The third way to address the dispersion phenomenon
is at the epitaxial level, by growing a thick capping layer on top of the AlGaN/GaN channel [161,162]. The
thick capping layer increases the distance from the surface to the channel, thus reducing the trapping effects
related to the surface states. The capping layer is usually combined with recessed gate technology to achieve
good gate control [163]. By effectively suppressing the gate leakage using fluorine plasma treatment of the
recessed gate region, 17.8 W mm−1at 4 GHz was achieved even without a SiNxpassivation layer [164].
Gate length scaling is the most straightforward way to push the operating frequency towards the Ka-band
(26–40 GHz) and beyond. Thus, a GaN HEMT utilizing a T-shaped gate with a small gate length of 160 nm
exhibited a power density of 10.5 W mm−1at 40 GHz with a power added efficiency (PAE) of 33% [166].
Furthermore, the optimization of the deposition condition of the gate dielectric and the plasma treatment
were proposed to passivate the surface states and reduce the gate leakage in HEMTs [167–170]. A HEMT
with a thin SiNxgate dielectric layer grown by plasma-enhanced atomic layer deposition (PEALD) showed a
significant reduction in reverse leakage and enhanced breakdown voltage, leading to a 7.16 W mm−1of
output power density and a PAE of 60.3% at 28 GHz [171].
While a shorter gate length works effectively to further scale down the GaN HEMT towards higher
frequency operation, a high aspect ratio (gate length to the gate-to-channel distance) must be maintained to
suppress the short-channel effect [172]. An AlGaN/GaN HEMT adopting a 6 nm AlGaN barrier and a 60 nm
gate length showed a current gain cut-off frequency (fT) of 190 GHz and a maximum oscillation frequency
(fmax) of 227 GHz [173]. However, changing the AlGaN barrier to a material with a stronger polarization
effect, such as InAlN and AlN, was predicted to achieve a higher frequency [174]. A fTup to 454 GHz has
been demonstrated with a 3.5 nm AlN barrier layer and 20 nm gate length [175]. The success of the
small-signal characteristics at these high frequencies is not the whole story, the large-signal performance,
including the output power and the PAE, must also be validated for a GaN HEMT. GaN HEMT technologies
utilizing the Ga-polar orientation have demonstrated good performance with 1.7 W mm−1of output power
density and 19.1% PAE at 95 GHz [176]. Similarly, at 86 GHz, a W-band Ga-polar GaN HEMT with an
output power of 3.6 W mm−1and 12.3% PAE was demonstrated [177].
With recent improvements in the epitaxial growth of N-polar GaN, N-polar GaN HEMTs have
demonstrated some of the highest power densities at mm-wave frequencies, outperforming their Ga-polar
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Figure 8. (a) Schematic structure of the double field plated GaN HEMT; (b) power sweep of the double field plated GaN HEMT
achieving 41.4 W mm−1power density at 4 GHz with 16 dB associated large signal gain and 60% power added efficiency (PAE)
[160]; (c) schematic structure of an N-polar GaN deep recess MIS-HEMT with atomic layer deposition Ru as gate metal; (d)
output power (Pout), linear transducer gain (GT), PAE, and drain efficiency (DE) measured as a function of input power (Pin) at
94 GHz with quiescent bias conditions of 500 mA mm−1IDS, Q and 18 V VDS, Q [165].
counterparts. The advantages of N-polar structures include higher scalability, lower resistivity ohmic
contacts, lower gate capacitance, and a more effective back barrier. 8 W mm−1output power at 94 GHz with
a PAE of 28.8% has been achieved in an N-polar GaN HEMT using a self-aligned foot gate process [178].
Atomic layer deposited (ALD) Ru was shown to effectively fill in the T-shaped gate trench to help realize
shorter gate length below 60 nm and minimize the gate resistance, giving rise to an output power density of
6.2 W mm−1with a high PAE of 33.8% at 94 GHz (figures 8(c) and (d)) [165]. A record-high 9.65 dB linear
transducer gain and demonstrated 42% PAE with associated 4.4 W mm−1of output power density at 94 GHz
have also been demonstrated for N-polar HEMTs on sapphire substrates [179].
2.3.2.2. Impact ionization avalanche time transit diodes (IMPATTs)
IMPATTs are powerful solid-state sub-THz sources in fundamental mode. When properly packaged, these
devices can replace elaborate amplifiers and multiplier chains and offer exceptionally high output power at
remarkably high frequencies. The output power in IMPATTs comes from the phase difference in voltage and
current, caused by the time delay from carrier avalanche multiplication and transition through the drift
region. To the first order, the operation frequency is inversely proportional to the thickness of the depletion
region (Wdep), determined by fopt =vsat
2Wdep , and the operation voltage is set by the critical field of the material.
Much higher performance is expected for GaN-based IMPATT diodes compared to Si and GaAs-based due to
their high critical field and high electron saturation velocity. Owing to the advancement of low dislocation
density bulk GaN growth, avalanche in GaN PN diodes is now more routinely achieved. Ji et al first
demonstrated a GaN IMPATT diode as a series resonant oscillator, showing an oscillation frequency at
800 MHz [180]. Limited by the avalanche current and the lack of a heat sink, the frequency was much below
the theoretical predictions. Later, Kawasaki et al mounted the GaN IMPATT diode on a copper heat sink in a
pill package and operated the device under 500 ns pulse mode (figure 9) [181]. The device showed a
maximum oscillation frequency of 9.5 GHz at a current density of 2.2 kA cm−2, offering a peak output
power of 14.45 mW. More recently, by decreasing the junction diameter and capacitance, more than 30 dBm
output power was achieved up to 21 GHz by Kawasaki et al [182]. Further reduction of the series resistance
and higher biasing current are expected to improve the device performance at higher frequencies.
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Figure 9. (a) Schematic view of a pill-packaged GaN IMPATT diode; (b) transient waveform for the input pulse bias during
operation; (c) output power spectrum at the input bias shown in (b) [181].
3. Aluminum gallium nitride/aluminum nitride (AlGaN/AlN)
3.1. Material properties
From GaN, we transition into the UWBG materials family starting with AlGaN, another III–V material.
AlGaN alloys with varying Al mole fractions are promising due to their tunable bandgaps spanning a wide
range, from 3.4 to 6.0 eV. The material band gap increases as Al composition increases until 100% to form
AlN. Higher critical electric fields can enable device operation with lower leakage current and higher
breakdown voltages [183–185]. Thus, AlGaN with higher a Al composition is of high interest. At the opposite
extreme of GaN, AlN has one of the widest direct bandgaps of 6.0 eV, generating significant attention for
applications in UV optoelectronics. The large bandgap of AlN leads to a high critical electric field of
15.4 MV cm−1, and a very high TC (highest reported 321 W (m·K)−1[186]), which is naturally appealing
for power and RF electronics as well.
Similar to GaN, a 2DEG is formed at an AlGaN/AlGaN interface (with two different AlGaN
compositions) without any intentional doping due to polarization-induced charges. The 2DEG mobility in
different AlGaN channels varies based on the Al composition of the channel, and the barrier material and is
dominated by alloy scattering. For example, MBE-grown HEMTs with Al0.06 Ga0.94N and Al0.15 Ga0.85 N
channels were reported to have 2DEG mobilities of 590 cm2(V·s)−1[187] and 430 cm2(V·s)−1[188],
respectively. While the mobility values are lower than in GaN 2DEG channels, higher breakdown voltages are
expected with increasing Al mole fractions [189]. For example, assuming the critical electric field of GaN to
be 3 MV cm−1,>9 MV cm−1was estimated for a 75% Al mole fraction AlGaN channel.
In AlN, the highest room temperature bulk electron mobility measured is 426 cm2(V·s)−1with a Si
doping concentration of 3 ×1017 cm−3, and 125 cm2(V·s)−1was achieved in more highly doped AlN
(1018 cm−3) [190]. Previously, the same group measured a value of only 125 cm2(V·s)−1at low doping
concentrations on the order of 1015 cm−3. The vast mobility improvement was attributed to the decreased
number of threading dislocations realized by suppressing the parasitic reaction of Al and N sources during
growth.
3.2. Growth and doping
3.2.1. Bulk AlN growth
Among the different polymorphs of AlN, the wurtzite crystal structure, first reported by Heinrich Otto in
1924, is most commonly studied for both bulk and epitaxially grown AlN [191]. For the growth of bulk AlN
single crystals, HVPE [192] and physical vapor transport (PVT) [193] are two of the most widely used
methods. Typically, AlN crystals are difficult to grow using common crystal growth methods such as pulling
and hot melt [194] due to their high melting point of 2800 ◦C and dissociation pressure of 20 MPa. While
both the HVPE and PVT methods have been utilized to grow thick AlN films with low screw dislocation
density (of the order 103cm−2) [195], HVPE growth is significantly slower in comparison to PVT methods
[196]. Thus, PVT methods are predominantly used in the growth of bulk AlN substrates due to their simpler
and safer growth process, faster growth rate, and good crystal integrity. Two PVT approaches are primarily
used: growth of thick AlN on 4H–/6H–SiC substrates [197–199] shown in figure 10(a) and spontaneous
nucleation followed by freestanding AlN growth [200,201]. A detailed study of PVT-AlN growth on SiC
templates for varying growth temperatures and orientations of SiC further exhibited that off-axis Si-face SiC
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J. Phys. Mater. 7(2024) 022003 K Woo et al
Figure 10. (a) Crucible design for spontaneous nucleation used for bulk AlN growth by physical vapor transport method [199];
(b) top view of grown AlN layer using sublimation growth method [194]; (c) symmetric (0002) and asymmetric (1 0¯1 5) x-ray
diffraction analysis (XRD) scans of AlN layers grown at various growth temperatures (1045 ◦C–1220 ◦C) with nucleation layer
(grown at 850 ◦C) with atomic force microscopy (AFM) surface morphologies at each temperature [205].
offers a flat morphology and better crystalline quality [202]. The largest AlN wafer prepared by PVT to date
is 40 mm in diameter with a low impurity concentration of <0.01% [197,203].
3.2.2. Epitaxial growth of AlN
To achieve epitaxial growth of AlN, several methods, including MOCVD, MBE, pulse laser deposition (PLD),
and sputtering have been demonstrated. The MOCVD method is suitable for mass production because of its
low deposition temperature and wide growth temperature range [204]. Using MOCVD, high-quality AlN
homoepitaxy with low background impurity concentration was demonstrated on single crystal AlN
substrates [193]. Thick (∼2µm), crack-free AlN growths with high crystalline quality, shown in figure 10(c),
were also achieved on sapphire substrates via a sandwich method [205] and by using a patterned sapphire
substrate [206]. Epitaxial lateral overgrowth-AlN layers with low crack and threading dislocation densities
have also been reported to grow on thin, stripe-patterned AlN seed layers directly deposited on Si (111)
substrates [207].
The epitaxial growth of AlN using MBE is limited to a slow growth rate; however, the growth process is
easier to control. Using MBE, the growth of AlN on a sapphire substrate was improved to yield a better
surface morphology via a nitridation step [208]. Additionally, smooth and strain-free AlN was grown by
MBE directly on a Si substrate with a nanowire template [209]. The PLD method is used for the growth of
thinner AlN films with good crystallinity and stoichiometry at relatively low temperatures of 800 ◦C [210,
211]. Under optimum growth conditions, a single-crystal AlN layer as thin as ∼1.5 nm was demonstrated on
a Si substrate [212]. For large-area deposition of AlN films, the sputtering method comes with the advantages
of a simpler process and lower cost. Using RF reactive sputtering, AlN layers were directly grown on a c-axis
sapphire substrate, and crystalline quality was found to improve with increasing nitrogen gas fraction during
reactive sputtering and RF power [213].
3.2.3. Epitaxial growth of AlGaN
Following the realization of high-quality GaN grown on low-temperature AlN buffer layers in 1986 [46], the
growth of AlGaN and AlGaN/GaN heterojunctions gained significant attention over the past three decades
with vast application prospects in high temperature, high power, RF, and optoelectronic devices [214–217].
AlGaN films were first grown as buffer layers for the growth of GaN or AlN epilayers. Following the
enhanced understanding of the growth mechanism and optimized growth process over the years, the quality
of the AlGaN films was improved by adopting epitaxial growth techniques such as MBE [218] and MOCVD
[219]. For example, an Al0.2Ga0.8N layer grown at 1050 ◦C was demonstrated with the insertion of
low-temperature AlGaN interlayers using MOCVD. This resulted in the simultaneous reduction of tensile
stress and crack formation, which is typically observed from the growth of high-temperature AlGaN directly
on GaN epilayers [220]. Fully relaxed, crack-free, 1.3 µm thick Al0.32Ga0.68 N layers were reported on
GaN-on-porous-GaN pseudo-substrates (figure 11(a)) [221]. Moreover, UID AlGaN epilayers graded over
Al compositions of 80%–90% and 80%–100% were also demonstrated using MOCVD [222]. Process
condition optimizations such as low temperatures and ammonia-rich conditions were used to increase the
growth rate of AlGaN up to 3.2 µm h−1[223]. Concurrently, the Al composition was found to be affected by
the growth temperature and growth rate.
The HVPE method is also used for the growth of AlGaN with low threading dislocation densities and
smoother surfaces. The epitaxial growth of Al0.10Ga0.90 N on an AlN/nanopatterned sapphire substrate
(NPSS) template by HVPE resulted in a low threading dislocation density of 1.4 ×109cm−2of the AlGaN
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Figure 11. (a) 20 ×20 µm2AFM height images of 1.3 µm Al0.32Ga0.68 N grown on 10 ×10 µm2tiles of compliant
pseudo-substrate [221]; (b) XRD scan patterns of the Al0.10Ga0.90 N grown on a conventional sapphire substrate (CSS) edge, CSS
center, and AlN/nanopattered sapphire substrate (NPSS) templates by HVPE [224]; (c) AlGaN guideline map and AlN growth
phase diagram for MBE. The black star indicates the buffer Al-rich AlN growth condition. Circles are the Al flux used in the
AlGaN layers, and triangles are the total metal flux (FAl +FGa) during AlGaN growth. The layer structures of the MBE-grown
AlGaN and AlN on the bulk AlN substrate are shown with the 2 ×2µm2AFM images of x =0.61, 0.86, and 0.89 Al content
UID-AlxGa1−xN grown on bulk AlN substrates [226].
epilayer owing to in-plane stress relaxation [224]. Further process optimization in HVPE such as etching to
suppress parasitic reactions was explored to achieve thick n-AlGaN cladding layers and free-standing AlGaN
substrates on both GaN and AlN templates [225]. MBE-grown AlGaN alloys with high mole fractions of Al
on single-crystal AlN substrates were also reported and shown in figure 11(c). For example, pseudomorph
AlxGa1−xN epitaxial layers with x∼0.6–1.0 were grown using MBE at a growth rate of 0.3 µm h−1[226].
3.2.4. Doping in AlGaN/AlN
For the successful adoption of UWBG materials in technologically relevant applications, doping and its
controllability are regarded as cornerstones. Doping of AlGaN is difficult to achieve compared to GaN, and
the ability to dope such alloys significantly decreases with increasing Al content. This can be attributed to the
fact that most dopant ionization energies increase with bandgap, therefore decreasing the fraction of free
carriers that are thermodynamically activated [3]. For AlGaN/AlN, doping strategies that exploit broken
crystal symmetries, such as polarization induced doping are useful for supplementing the traditional
chemical substitutional doping. Modulation doping is also utilized for enhancing the number of confined
carriers in the material system. Several p-type doping approaches, such as superlattice doping [227], Mg
delta doping [228], and Mg–Si alternative co-doping [229] have been investigated for improving the doping
efficiency of Al-rich AlGaN. Using Mg delta doping, a hole concentration of 8.3 ×1018 cm−3with Mg
doping concentration of 1.6 ×1019 cm−3was achieved, indicating a doping efficiency of up to 51.9% [230].
On the other hand, Si is primarily used as the n-type dopant for AlGaN with high Al content [231], including
AlN. For example, Taniyasu et al demonstrated n-type conduction in Si-doped AlN showing a room
temperature Hall mobility of 426 cm2V−1s−1and electron concentration of 7.3 ×1014 cm−3. The study
also demonstrated p-type conduction in Mg-doped AlN with a Mg concentration of 2 ×1020 cm−3and
thermally annealed at 800 ◦C for 10 min. Beyond 2 ×1020 cm−3concentrations, Mg doped AlN becomes
highly resistive due to a self-compensation effect [232], a phenomenon also found in n-type Si doped AlN.
Typically, an increase in the Si content leads to an increase in free electrons; however, this trend does not
continue at higher doping levels. A further increase in the Si concentration leads to a decrease in the free
electron concentration, commonly referred to as the compensation knee [232–234]. A variety of
compensating defects can be the culprit, but the mechanism and identity of these defects have not been
conclusively determined yet. Researchers have tried different dopants as well, and successful experimental
achievement of both n-type AlN:Si films using the metal modulated epitaxy (MME) method and p-type
AlN:Be films was demonstrated [235].
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Figure 12. (a) Schematic illustration of the p-InGaN/i-AlxGa1−xN/n-AlxGa1−xN diode structure; (b) forward I–V characteristics
of the diodes with different Al compositions at RT [236]; (c) schematic illustration of a Al0.3Ga0.7N PN diode and (d) reverse
current–voltage characteristics of the Al0.3Ga0.7 N PN diode showing breakdown voltage of 1627 V (inset—an optical image of
processed diode with 50 µm diameter p-contact metal) [237].
3.3. AlGaN devices and applications
3.3.1. High power devices
3.3.1.1. PIN diodes
The larger bandgaps of AlGaN compositions are promising for offering extremely low reverse leakage
currents and exceptionally high breakdown voltages in AlGaN-based PIN diodes. In 2006, Nishikawa et al
demonstrated metal-organic vapor phase epitaxy (MOVPE)-grown AlGaN PIN diodes with intrinsic layers
of unintentionally doped Al0.13Ga0.87N and Al0.22Ga0.78 N, separately [236]. The PIN structure was grown on
a conductive n-SiC substrate and capped by a p-InGaN layer that helped to reduce the ohmic contact
resistances. Using only a ∼225 nm thick intrinsic layer, the Al0.22Ga0.78N diode offered a breakdown voltage of
78 V with an on-resistance of 1 mΩ·cm2, while the reference GaN diode exhibited a lower breakdown voltage
of 54 V (figures 12(a) and (b)). The corresponding critical electric fields were calculated to be 3.5 MV cm−1
and 2.4 MV cm−1, respectively, assuming the intrinsic layer was fully depleted. In 2007, the same group
reported another PIN diode with an intrinsic layer of Al057Ga0.43N (225 nm), showing 185 V breakdown
voltage resulting in a critical electric field of 8.1 MV cm−1. The maximum BFOM was shown with 30% of Al
composition because of the tradeoff between breakdown voltage and on-state resistance and is twice as high
as that for GaN-based diodes, showing promise for high-power operation in AlGaN-based devices [214].
In 2016, MOVPE-grown Al0.3Ga0.7N quasi-vertical PN diodes on a non-conductive sapphire substrate
were reported where a remarkably low reverse leakage current of <3 nA was achieved. The breakdown
voltage for this diode was 1600 V with an estimated critical electric field of 5.9 MV cm−1(figures 12(c) and
(d)). As a comparison, an ideal planar GaN PN diode with the same breakdown would require a
∼7µm-thick drift region with a background carrier concentration of <2.4 ×1016 cm−3[237]. A specific
on-resistance of 16 mΩ·cm2was reported at a current density of 1.5 mA cm−2. The relatively high resistance
was a consequence of the n-type contact layer in the front-contacted device geometry, but comparable with
14 mΩ·cm2reported for a GaN PN diode grown on sapphire [238].
3.3.1.2. HEMTs
In power electronics, vertical device structures are typically favored for areal efficiency and elimination of
surface state effects. Nonetheless, lateral device structures in U/WBG materials are still important, as seen in
GaN-channel HEMTs, due to the advantage of higher channel mobility. Previously, the role of AlGaN in
AlGaN/GaN HEMTs was introduced. Here, only fully AlxGa1−xN structures will be discussed. Both lateral
and vertical AlGaN device structures are still in their infancy, but lateral devices are more readily achievable
due to existing bulk growth limitations. The growth and device optimization of AlGaN channel HEMTs have
been reported in several studies. A HEMT structure of Al0.53Ga0.47 N/Al0.38Ga0.62 N achieved a maximum
breakdown voltage of 1650 V with a gate to drain distance of 10 µm [215]. In 2010, an AlGaN-channel
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Figure 13. (a) Schematic of all-AlGaN N-polar HEMT device with an Al0.20 Ga0.80N channel layer and an Al0.30Ga0.70 N channel
layer; (b) the simulated band diagrams of Al0.20Ga0.80 N channel and Al0.30Ga0.70 N channel HEMTs. (c), (d) XRD spectra (2θ-ω
scan of (002) plane) of these structures, confirming the stoichiometries of all-AlGaN HEMT structures [189].
HEMT with a high Al composition of over 0.5 (Al0.51Ga0.49N) was first reported. The HEMT structure was
grown on a free-standing AlN substrate to improve crystalline quality, and the fabricated device exhibited a
maximum drain current of 25.2 mA mm−1and a breakdown voltage of 1800 V [239]. A metal stack,
composed of Zr/Al/Mo/Au, was found to show low contact resistivity for source and drain ohmic contacts
for AlN/AlGaN HEMT with AlN as a barrier layer. This HEMT also demonstrated low degradation of drain
current at temperatures from 300 K to 573 K showing stable high-temperature operation [240]. An
Al0.85Ga0.15 N channel HEMT was demonstrated in 2016 showing a very low off-state leakage current of
10−7mA mm−1. The device’s reported breakdown was 810 V, which corresponds to an average field of
0.81 MV cm−1. This is only a fraction of the predicted critical electric field in Al0.85Ga0.15N (13 MV cm−1),
due to the immature state of the material [216]. Although most of the reported efforts discuss the
investigation of metal polar AlGaN channel based HEMT structures, very recently MOCVD-based growth of
N-polar AlGaN channel HEMT structures with varying Al mole fractions in the AlxGa1−xN channel has been
demonstrated [241]. The N-polar all-AlGaN HEMT with 0.2 Al in the channel and 3 µm channel length
offered a drive current of 375 mA mm−1while maintaining a low on-state leakage current of ∼0.5 nA mm−1
and >400 V breakdown voltage [189], promising for high power electronic applications (figure 13).
3.3.2. RF HEMTs
AlGaN channel based HEMT structures as high-frequency devices have shown significant advancement in
the last decade. Raman et al demonstrated a low Al composition Al0.06Ga0.94N channel HEMT, which showed
an fTof 13.2 GHz and fmax of 41 GHz. At 4 GHz, the output power was 4.5 W mm−1demonstrating the
potential of AlGaN channel HEMTs for high-voltage switching and microwave power applications [242].
Bajaj et al demonstrated nearly constant fTand fmax profiles in a scaled graded-AlGaN (0%–30% Al)
channel with an fTof 52 GHz and an associated fmax of 67 GHz, and the demonstrated flat fTand fmax
profiles could help to improve the linearity performance of devices [243]. With a linearly graded AlGaN
channel polarization doped field effect transistor (PolFET), X-band power and linearity performance were
reported for the first time in 2018 with a third-order output intercept (OIP3) of 33 dBm, and OIP3/PDC (DC
power consumption) of 3.4 dB [244]. In 2020, Xue et al reported an Al0.65Ga0.35N/Al0.4 Ga0.6N HEMT with a
current density of 900 mA mm−1,fTof 20 GHz, and fmax of 36 MHz. The off-state breakdown voltage in
these devices was 80 V with 1 µm gate to drain separation and a gate length of 100 nm [217]. The same
group demonstrated an exceptionally low gate leakage current density of 1.4 ×10−8mA mm−1even at a
high forward gate bias of VGS of 12 V, and a current on/off ratio >1010 was achieved simultaneously. Small
signal measurement showed that the device has an fTof 3.8 GHz and fmax of 4.5 GHz for the same Al
compositions [245].
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J. Phys. Mater. 7(2024) 022003 K Woo et al
Figure 14. RF performances of a HEMT with an 80 nm gate with both source-to-gate and gate-to-drain spacings of 500 nm: (a)
the small-signal gain performance at VGS =2.75 V and VDS =20 V; (b) the 3 GHz class A power sweep for a 2 ×50 µm2HEMT
biased with VGS =3.75 V and VDS =20 V [248]. Here, the power gain (Gp), transducer gain, output power, and power-added
efficiencies are plotted as a function of input power.
The RF operation of AlGaN channel transistor with Al-composition above 80% was first reported in
2018 demonstrating an impressive current density of 265 mA mm−1for a gate length of 0.8 µm. The
reported fT/fmax were 5.4/14.2 GHz respectively [246]. An Al0.75Ga0.25N/Al0.6 Ga0.4N HEMT was also
reported with a drain current density (ID, max) of 460 mA mm−1for a gate length of 130 nm. The small signal
measurement showed a current/power gain cutoff frequency (fT/fmax) of 40 GHz/58 GHz [247]. Also,
Al0.85Ga0.15 N/Al0.7Ga0.3 N HEMT with 80 nm gate was reported to display a maximum current of
160 mA mm−1with fTof 28.4 GHz and fmax of 18.5 GHz (figure 14) [248].
3.4. AlN devices and applications
3.4.1. High power devices
3.4.1.1. Schottky barrier and PN diodes
In 2015, thick n-type AlN layers were homoepitaxially grown by HVPE on AlN (0001) seed substrates, and a
SBD was fabricated using Ni/Au Schottky contacts. High rectification with a turn-on voltage of
approximately 2.2 V was observed along with a reverse breakdown voltage of >550 V [249]. Maeda et al
reported an AlN quasi–vertical SBD fabricated on an AlN bulk substrate. An undoped AlN layer, a Si-doped
Al0.9Ga0.1 N current spreading layer, and an AlN buffer layer were grown by plasma-enhanced MBE. This
device was reported to withstand at least 100 V reverse breakdown voltage; however, the on-resistance was
high (1.8 Ω·cm2) [250]. In 2017, Fu et al were the first to demonstrate 1 kV-class AlN SBDs on sapphire
substrates grown by MOCVD. The device showed a low turn-on voltage of 1.2 V, a relatively high on/off ratio
of ∼105, and a low reverse leakage current <1 nA. The devices also exhibited excellent thermal stability over
500 K and a breakdown voltage of ∼1 kV without any use of additional edge termination methods
(figures 15(a) and (b)) [251]. Researchers have demonstrated few AlN-based PIN diodes as the challenge of
growing thick AlN layers remains a primary obstacle in addition to difficulties in doping. Recently, however,
an AlN PN diode with a nearly ideal turn-on voltage of ∼6 V was demonstrated with a hole concentration of
3.1 ×1018 cm−3and an electron concentration of 6 ×1018 cm−3[235].
3.4.1.2. Metal–semiconductor field effect transistors (MESFETs)
In 2022, Hiroki et al reported the first AlN MESFET with epitaxially grown n-type AlN channel layers and
achieved an off-state breakdown voltage of 1.72 kV with a 16 µm channel gate to drain distance. This result
was attributed to the growth of comparatively low defect AlN using a high-temperature MOCVD with a
uniquely designed reactor. To achieve good ohmic contacts, a graded AlGaN layer between AlN and metal
electrodes was used. With increasing temperature from room temperature to 500 ◦C, both on-current and
transconductance increased while maintaining a small reverse leakage current of 1.6 ×10−11 A mm−1,
leading to a large on/off ratio of ∼105even at 500 ◦C. The results indicate that AlN MESFETs with epitaxially
grown n-type AlN channel layers are promising for high-voltage applications at high temperatures
(figures 15(c)–(e)) [233].
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J. Phys. Mater. 7(2024) 022003 K Woo et al
Figure 15. (a) The schematic view of the AlN SBD grown on sapphire by MOCVD and (b) the forward I–V characteristics at
different temperatures, which demonstrated 1 kV breakdown voltage [251]; (c) schematic view of the first demonstrated AlN
metal–semiconductor field-effect-transistor, (d) the breakdown characteristics for a 16 µm gate-drain length device, and (e) the
breakdown voltage as a function of gate to drain length [233].
4. Diamond
4.1. Material properties
As depicted in figure 1(a), diamond has outstanding properties across the board for power and high
frequency electronics. Diamond has an indirect band gap of 5.47 eV with an expected ultra-high critical field
of >10 MV cm−1at which point it would theoretically breakdown by the avalanche phenomenon [252,253].
Indicators for avalanche breakdown have been observed by Ohmagari et al in PIN diodes which exhibited
positive temperature coefficients [254]; however, the observation has not been widely reproduced and
further studies are required to better understand the phenomenon.
While high critical field values are expected in all UWBG materials, diamond is unique in that it has both
high electron and hole bulk mobilities, unlike in GaN and Ga2O3. Using time-of-flight experiments, low field
drift mobilities of 3500–4500 cm2(V·s)−1and 2600–3800 cm2(V·s)−1were extracted for electrons and
holes, respectively, and carrier lifetimes were estimated to be >2µs. The high mobilities were attributed to
the high-quality growth of homoepitaxial CVD diamond [255]. These values have been pushed even higher
by the extrapolation of time-resolved cyclotron resonance measurements of ultrapure diamond to room
temperature. This yielded record high mobilities of 7300 and 5300 cm2(V·s)−1for electrons and holes [256].
While spectacularly high values have been reported, the average Hall hole mobility measured in boron doped
diamond decreases with increasing doping density and temperature. With boron doping concentrations on
the order of 1015–1017 cm−3, simulated hole mobilities are ∼2000 cm2(V·s)−1, and experimental values fall
between 1000 and 2000 cm2(V·s)−1. From 1018–1020 cm−3, the mobility decreases from 1000 to
30 cm2(V·s)−1[257]. In n-type diamond, phosphorous doped diamond from 1015–1017 cm−3is simulated
to have mobilities ∼1000–200 cm2(V·s)−1and decreases to below 30 cm2(V·s)−1above 1018 cm−3[258].
The velocity field curves for electrons and holes were shown to be similar at room temperature [259] with
the saturation velocity of electrons and holes to be on the order of 1.4–2 ×107cm s−1at an electric field of
105V cm−1[260,261].
Moreover, diamond’s extremely high TC makes it stand out among other UWBG materials. Due to
diamond’s strong covalent C–C bonding yielding a bond length of only 1.54 Å, heat is effectively dissipated
through lattice vibrations with low phonon scattering. As a result, diamond has one of the highest thermal
conductivities of semiconductors and insulators, >2200 W (m·K)−1, which is 5 times greater than even that
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Figure 16. (a) General growth chemistry of MPCVD diamond growth using primarily CH4gas and H2plasma [263]; (b)
Schottky barrier diodes fabricated on a mosaic diamond substrate [254]; (c) the largest diamond substrate to date grown by
heteroepitaxial methods [266].
of copper, a common heat sink material. Isotopically enriched (using 13CH4or 12CH4) diamond has shown
thermal conductivities up to 3300 W (m·K)−1[262].
4.2. Growth and doping
4.2.1. Single crystalline bulk substrate growth
While the superior properties of diamond make it an attractive candidate for future high power and
frequency device platforms, manufacturing large-diameter, high-quality diamond substrate remains a
challenge. The high-pressure high-temperature technique can be employed to synthesize low defect density
diamond crystals; however, this method is inherently limited to <1 cm2diamond sizes. Alternatively,
microwave plasma chemical vapor deposition (MPCVD) methods are prominently used to enlarge seed
crystals by outward or lateral growth. Activated atomic hydrogen from the H2gas precursor reacts with the
hydrogen-terminated surface of a diamond seed to provide a reaction site for carbon radicals to bond to. The
CH3
+carbon radicals are supplied from CH4gas and generated using a plasma or high temperature
environment in the chamber [263]. By this chemistry, monolayers of carbon are progressively deposited on
the surface, as illustrated in figure 16(a). Unfortunately, this growth process is limited by the formation of PC
diamond at the rim which can lead to further stress and cracking of the substrate [264]. Researchers have
explored methods to suppress PC diamond formation, such as with modified pocket holders, different
diamond seed geometries, and varying growth parameters. These efforts have produced substrates still on the
order of 1 cm in diameter [265]. 2 inch substrates were realized by Yamada et al (figure 16(b)) by
homoepitaxially growing diamond by CVD on a mosaic of smaller clone substrates grown from the same
seed crystal, however high defect densities were present at the coalescence boundaries [252]. More recently,
Ohmagari et al demonstrated the benefit of a W buffering layer in mitigating threading dislocations for
mosaic diamond substrates [253] and showed very similar performance to Schottky diodes fabricated on and
off the boundaries [254]. Finally, another method to achieve larger area diamond substrates is by
heteroepitaxial growth of diamond on materials with readily available substrates. Schreck et al demonstrated
heteroepitaxial diamond growth on an Ir/YSZ/Si (001) substrate producing a 1.6 mm thick diamond layer
with a diameter of 92 mm as pictured in figure 16(c) [266]. The use of negative voltages during the
bias-enhanced nucleation process and selection of Ir as the substrate, were key in enabling single-crystalline
diamond formation. While the diamond substrates grown in this and other more novel methods have shown
immense progress, the quality is certainly still lacking. Thus, continued progress in developing larger-scale
diamond growth is critical for the practical widespread adaption of diamond as a semiconductor material.
4.2.2. Doping
In diamond, p-type doping using boron dopants can be readily achieved during bulk MPCVD diamond
growth. For boron dopant concentrations up to 1018 cm−3, boron has a relatively large activation energy of
0.37 eV, which decreases to ∼0.06 eV when boron concentration exceeds 1020 cm−3according to Pearson
and Bardeen’s model. Furthermore, at concentrations >1019 cm−3, hopping conduction, between ionized
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J. Phys. Mater. 7(2024) 022003 K Woo et al
Figure 17. (a) Theoretical and experimental bulk hole mobility using various measurement methods; (b) 2DHG hole mobilities
measured from various diamond orientations and passivation materials [280] (and references therein).
and neutral acceptors, dominates the conduction mechanism [267]. Thus, incomplete ionization and
varying conduction mechanisms must be considered when designing devices.
On the other hand, n-type doping in diamond has been more difficult to achieve. Successful
phosphorous doping with n-type conductivity was first measured in 1996 by Koizumi et al using phosphine
as the dopant source during MPCVD growth [268]. Follow up growth optimizations yielded n-type diamond
thin films grown on (111) Ib substrates with a maximum mobility of 240 cm2(V·s)−1and an activation
energy of ∼0.6 eV [269]. Due to the relatively high activation energy, phosphorous is not readily ionized at
room temperature, with ionization levels of only 10−5–10−6[270]. To realize lower resistance n-type
diamond, on the order of 70 Ω·cm, heavy phosphorous doping of diamond >1020 cm−3is required to lower
the activation energy through hopping conduction [271]. On the other side of the spectrum, fine n-type
doping control was shown with phosphorous concentrations <3×1017 cm−3. The study reported n-type
conductivity of the lowly doped films (2 ×1015 cm−3) with high RT mobility of 1060 cm2(V·s)−1[272].
While phosphorous is most readily incorporated into substitutional sites in (111) diamond, 2–3 orders
higher than in (100), the high defect density formed during growth creates issues in device performance.
More recently, the (113) orientation was also found to be a stable plane for phosphorous doped epilayer
growth in addition to boron doped. In the study, the homoepitaxial layers reached up to 4.5 ×1019 cm−3
phosphorous content, greater than that of (100) and less than that of (111), proving to be a promising avenue
for phosphorous doping in the future [273].
4.2.3. Surface transfer doping by hydrogen termination
While p-type boron doping is accessible in diamond, the high activation energy allows only a small fraction
of dopants to ionize, making it difficult to engineer highly conducting channels in devices [274]. It was
discovered that when hydrogen-terminated diamond, which has a negative electron affinity, is exposed to air
containing atmospheric adsorbates, a two-dimensional hole gas (2DHG) forms near the surface. This p-type
surface hole accumulation layer typically has a sheet charge density of 1012–1013 cm−2and hole mobility of
20–200 cm2(V·s)−1[274]. In efforts to identify the key molecule responsible for forming the 2DHG, it was
found that exposing the diamond to increasing levels of NO2led to an increased hole concentration, up to
2.3 ×1014 cm−2, and conductivity [275]. At high temperatures above 300 ◦C, the 2DHG formed from just
atmospheric adsorbates was discovered to be unstable, so researchers employed an Al2O3passivation layer to
stabilize the 2DHG at temperatures up to 500 ◦C [276]. Since then, other dielectric materials have been
studied to passivate H-terminated diamond as well. More recently, transition metal oxides (TMO),
particularly MoO3[277] and V2O5[278,279] have shown superior hole carrier concentrations on the order
of 1014 cm−2. With its high carrier density, the 2DHG has become a pathway for the most prominent
diamond transistor, the H-terminated FET. However, an inverse relationship between hole sheet density and
mobility has been repeatedly shown (figure 17), and thus a significant increase in conductivity may be
limited. Charged surface acceptors and disorder related to the C–H surface dipoles have been proposed as
mobility-limiting mechanisms [274], but more research is critical to determine whether the mobility
limitations can be overcome to produce higher-performing devices.
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Figure 18. The cross-section schematic of vertical diode structures in diamond: the (a) vertical Schottky (VSBD); (b)
pseudo-vertical Schottky (pVSBD); (c) Schottky PN; (d) PIN diode.
4.3. Diamond devices and applications
4.3.1. High power devices
4.3.1.1. Schottky and PN diodes
As diamond lacks a reliable n-type dopant, the p-type SBD is the most mature diamond diode device. Prior
to the wider availability of low resistance diamond substrates, pseudo-vertical Schottky diodes were primarily
fabricated on doped epilayers with an insulating substrate (figure 18(b)). With the development of highly
boron doped substrates, true vertical Schottky diodes are now commonly reported as well (figure 18(a)). The
Schottky barrier height can be varied in diamond diodes by utilizing different Schottky contact metals. It was
shown that diodes with greater barrier heights can yield lower leakage [281], which comes with a cost of
increased on-resistance. Diodes using Schottky contact metals of Al [281,282], Ni [282,283], Mo [281], Pt
[281], Au [282,284,285], Ag [283], WC [286], Zr [287], etc have demonstrated Schottky barrier heights to
diamond ranging from <1 to 3.4 eV. Various surface terminations techniques can vary the Schottky barrier
height as well. In the case of a hydrogen-terminated diamond surface, the p-type conductivity at the surface
must be removed to prevent a leakage path from forming. With oxygen-terminated surfaces, on the other
hand, the metal contact becomes rectifying. Thus, increased oxygen termination at the surface was found to
increase the Schottky barrier, reduce reverse leakage, and increase breakdown [284,288,289]. Diamond
surfaces are commonly oxidized by boiling in strong acid mixtures and/or by ultraviolet (UV)/ozone
treatment during Schottky diode fabrication [290]. The oxygen content on the diamond may be varied by
the wet chemical acids, treatment time, and temperature as well as the ozone concentration and treatment
time for UV/ozone [282].
Diamond Schottky diodes have primarily reported breakdown electric fields of <4 MV cm−1even with
field termination structures such as field plates. Select works have shown a breakdown field of 7.7 MV cm−1,
the record in diamond devices. Traoré et al reported results measured from pseudo-vertical Schottky diodes
with oxidized Zr Schottky contacts that resulted in a record 244 MW cm−2BFOM [287]. Volpe et al
demonstrated the high breakdown voltage capability of diamond using Au Schottky contacts to a 13.6 µm
p-epilayer (3 ×1016 cm−2boron doped), and set a record breakdown voltage of 10 kV [285]. In recent
works, pseudo-vertical Schottky diodes have also been demonstrated on (113) orientated surfaces, with
similar performance to that of (100) [291]. The (113) orientation is of interest as it has shown less surface
roughness than (111), thus providing better interface qualities while being relatively favorable for both boron
and phosphorous doping.
In 2009, Makino et al demonstrated an alternative unipolar diode, the Schottky PN diode (SPND). In this
configuration, the Schottky metal contacts a lightly phosphorous doped n-type layer on a p+layer
(figure 18(c)) [292]. As a result, the n-type layer is fully depleted in the forward and reverse modes, and the
diode conducts like a p-type Schottky diode in the forward bias region, enabling fast switching speeds. In the
reverse bias region, the maximum electric field is primarily blocked by the n-region (figure 19). This
theoretically enables a more highly doped p-type region, thus increasing the forward current density while
maintaining a sufficiently thick space charge region to block high voltages in the reverse region due to the
n-type region. Using the SPND structure, a record low on-resistance of 0.03 mΩ·cm2was achieved with a
breakdown field of 3.4 MV cm−1and a breakdown voltage of 55 V yielding ∼100 MW cm−2BFOM [293]. A
>1 kV SPIND was later demonstrated by Dutta et al [294] and an ultrahigh forward current density on the
order of 105A cm−2by Surdi et al [295], showing the overall potential of the SPIND for high power
applications.
Furthermore, high temperature measurements in Schottky diodes have been measured up to 1000 ◦C
and showed a rectification ratio of up to 104at 600 ◦C [283,288]. As the temperature increases, the forward
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J. Phys. Mater. 7(2024) 022003 K Woo et al
Figure 19. Proposed band diagrams of the SPND at (a) thermal equilibrium, (b) forward bias, and (c) reverse bias based on
experimental results [292].
current density increases as the result of boron dopant ionization, which overtakes the decrease in mobility
[283,288,296]. In high temperature measurements, it is also generally observed that an increase in Schottky
barrier height and decrease in ideality factor occurs, indicating barrier inhomogeneity. This has been
reported in other WBG materials as well [286], and further supported by conductive AFM measurements
which showed that a very small fraction of the contact was active in the lower voltage range of the forward
bias region [296].
Due to the challenge of n-type doping, PN diodes are relatively underdeveloped. Several studies have
demonstrated PN diodes, with a focus on UV light emission indicating bipolar transport; however, the
electronic performance is lacking. Due to the high resistivity of n-type diamond, the on-state current density
remains limited, with 140 A cm−2as the highest reported, while a reverse blocking voltage up to 920 V [297]
and breakdown field of 3.9 MV cm−1[294] have been achieved.
The current breakdown field values are still far from theoretical predictions in diamond, so efforts to
reduce reverse leakage current and premature breakdown are highly relevant. The reverse bias leakage
current in Schottky diamond diodes has been fit to the thermionic emission model with image-force
lowering at lower fields, and the thermionic field emission model at fields >1 MV cm−1[286,298]. While
this observation has been common in other wide-bandgap semiconductors as well, another prominent
source of leakage is the presence of defects formed during growth, which can affect any type of device. These
include non-epitaxial crystallites, which have been characterized as killer defects [298], and crystallographic
defects like threading dislocations. In a study of PIN diodes, the reverse bias current characteristics, analyzed
up to 150 ◦C, were attributed to hopping conduction and Poole–Frenkel emission through threading
dislocations [299]. Furthermore, it was found that as the drift layer increases in thickness, the breakdown
field does not proportionally increase in most cases, which indicates poorer epitaxial quality with thicker
drift layer growth [300]. While the reduction of defects requires improvement in growth techniques, a
common cause for reverse breakdown and increased leakage is field enhancement at the edge of the
electrode, a common issue in other materials as well. In response, field-plated Schottky diodes with sputtered
Al2O3were studied and found to increase the breakdown voltage appreciably by more than 2 times, from
0.6–0.8 to 1.6–2.0 MV cm−1[301,302]. While the impact of the field plate has been experimentally shown,
more recent studies have not reported similarly effective field plates. Other edge termination structures such
as ramped field plates, junction termination, etc have yet to be successfully demonstrated in diamond due to
fabrication limitations such as selective doping. Thus, in diamond two-terminal devices, there is still
significant room for optimization, improved performance, and reliability studies, which should naturally
follow the development of improved growth and doping techniques.
4.3.1.2. MESFETs and MOSFETs
In oxygen terminated diamond, FETs can be fabricated which rely on bulk conduction in the channel as
illustrated in figures 20(a)–(c). Due to the large Schottky barrier heights achievable in diamond on
oxygen-terminated diamond, MESFETs have been studied with relatively low gate leakage. Umezawa et al
demonstrated diamond Pt-gated MESFETs with increasing breakdown voltages from 693 V to 1530 V as
gate-to-drain distance was increased from 5 to 30 µm [303]. The less-than-ideal breakdown field,
approximately 2.15 MV cm−1, can be attributed to electric field spiking at the drain-side edge of the gate
electrode. Another FET structure that has been demonstrated is the deep depletion mode MOSFET by Pham
et al [304,305]. The structure utilizes an Al2O3dielectric and has achieved a high hole mobility in the
conducting channel of 1000 ±200 cm2(V·s)−1. This structure has the potential to take advantage of bulk
hole mobility while limiting gate leakage which is typically higher in MESFETs.
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J. Phys. Mater. 7(2024) 022003 K Woo et al
Figure 20. The cross-section schematic of FET structures in diamond categorized into oxygen-terminated diamond FETs and
hydrogen-terminated diamond FETs.
While more difficult to achieve due to the challenge of n-type doping and the WBG of diamond, classic
inversion channel MOSFETs have been shown due to improvements made in phosphorous doping. Such
devices have advantages in gate controllability and threshold voltage tunability [306]. In 2016, Matsumoto
et al reported the first inversion p-channel diamond MOSFET with normally-off characteristics utilizing a
phosphorous-doped n-type body grown on a (111) substrate. A high-quality interface by wet annealing was
formed between the Al2O3gate oxide and O-terminated n-type diamond. The devices with a gate length of
5µm delivered a maximum drain current density of 1.6 mA mm−1, an on/off ratio >1010, and a field-effect
mobility of 8.0 cm2(V·s)−1. The low mobility was attributed to high interface defect density, which can be
reduced by achieving flatter surfaces [306]. Further studies showed that decreased phosphorous doping
density (2 ×1015 cm−3) resulted in greater smoothness and lower interface defect density, and as a result,
higher mobility, up to 20 cm2(V·s)−1and higher drain current density [307]. Thus, the interface state
density between the n-type diamond and the oxide must be further studied and reduced to improve the
performance of inversion channel MOSFETs. More recently they also demonstrated an inversion p-channel
MOSFET on nitrogen doped diamond, which is much easier to dope albeit has a much larger activation
energy, 1.7 eV. Nonetheless, the MOSFET exhibited a drain current density very similar to that of MOSFETs
fabricated using a phosphorus n-type diamond body [308].
Hydrogen-terminated (H-term) FETs are the most studied diamond transistor, in which the surface
2DHG formed by hydrogen termination of single-crystalline (SC) or PC diamond generates a conductive
channel with a high density of hole carriers (figures 20(d) and (e)). In an H-term MESFET, a Schottky
contact, commonly Al, is directly deposited on the diamond as the gate metal. In a MOSFET, Al2O3is often
used as the gate oxide since it preserves the 2DHG and stabilizes it for high temperature operation. A
NO2-enhanced H-term MOSFET showed the highest reported breakdown voltage to date, 2.6 kV at a field of
2 MV cm−1[309]. The highest drain current density is reported to be 1.35 A mm−1using NO2exposure to
increase hole density and Al2O3passivation [310].
Because the 2DHG consists of surface charges formed by hydrogen termination, it is very sensitive to the
surface and interface quality. H-term FETs may be depletion or enhancement mode devices based on the
surface treatment of diamond and interface defects. To form enhancement mode devices, several strategies
have been employed such as selecting low work function gate material [311], partially oxidizing the
H-diamond surface [312,313], and choosing gate oxides with different deposition methods [314–316]. The
highest current density for enhancement mode devices, 400 mA mm−1, was recently reported by Zhu et al
using PC diamond MOSFETs with a heavily boron-doped layer as the source/drain region [315].
While Al2O3is the most popular dielectric used, many others have been studied as well such as HfO2and
h-BN [314]. Exfoliated single crystalline h-BN is known to have a very flat surface with few charged
impurities and no dangling bonds. Thus, it has the potential to form a high-quality interface with diamond.
Recently, Sasama et al used a h-BN gate insulator which resulted in a >300 cm2(V·s)−1channel mobility
device [317]. The high mobility was attributed to the low density of defects in h-BN, and follow-up studies
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J. Phys. Mater. 7(2024) 022003 K Woo et al
Figure 21. (a)–(c) The schematic and microscope images of an RF diamond H-term MOSFET; (d) large-signal performance of (a)
at VDS =−50 V [324].
were able to further enhance the mobility to 680 cm2(V·s)−1by eliminating air exposure between the
hydrogen termination and h-BN lamination steps during fabrication [318].
4.3.2. RF hydrogen terminated FETs
Around 2001, researchers first began to report on the high-frequency performance of H-term FETs; however,
high-frequency devices in diamond are still very much in the early stages of development. A series of studies
from Kasu et al culminated in a device (gate length =0.1 µm, width =100 µm) yielding 2.1 W mm−1
output power density [319]. This relatively high value in diamond was attributed to the high-purity gas used
during homoepitaxial layer growth. Later, the group demonstrated a MESFET (gate length =0.4 µm,
width =1 mm) with a record 23.2 dB maximum power gain and 56.3% PAE [320] measured at 1 GHz and
drain-to-source voltage (VDS)=−20 V. Published in the mid-2000s, these RF measurement values remain
difficult to surpass. While SC diamond is typically preferred for more ideal electronic properties, PC
diamond is much more accessible, offering lower costs and larger diameters, and is also actively studied for
fabricating H-term FETs. MESFETs fabricated on preferentially (110) oriented PC diamond by Ueda et al
demonstrated a high fTof 45 GHz and fmax of 120 GHz and leakage was not observed in the large grain
(100 µm) PC diamond substrate [321].
In 2007, Hirama et al measured the RF characteristics of H-term MOSFETs on SC and PC diamond using
an alumina gate insulator for the first time [322]. The gate oxide was formed by the oxidation of 3 nm thick
Al. The (001) homoepitaxial devices demonstrated a similar output power density to that of Kasu et al, with
2.14 W mm−1at 1 GHz. Furthermore, the PC (110) devices yielded higher current density and 1.5 times the
fTthan the SC (001) devices. This was attributed to the differing orientations rather than the PC and SC
nature of the substrates. Previous reports have shown that H-terminated (110) diamond resulted in higher
C–H bond density and thus higher hole densities in the 2DHG.
In recent studies, Yu et al reported the highest fT/fmax in diamond MOSFETs of 70/80 GHz, which was
attributed to continued scaling of the source-drain distance and thin 6 nm gate oxide [323]. Then in 2019,
Imanishi et al demonstrated the highest power density at 1 GHz to date, 3.8 W mm−1in a MOSFET
diamond device with 100 nm ALD Al2O3on a (110) preferential PC diamond substrate (figure 21) [324]. In
2022, the highest RF power densities were measured at 2, 4, and 10 GHz to date: 4.2, 3.1, and 1.7 W mm−1,
respectively, on homoepitaxial (001) single crystalline diamond substrates with 100 nm Al2O3[325]. In both
these studies, VDS was pushed to greater than 40 V, which contributed to the record power densities
measured in diamond.
4.3.3. Heterogeneous integration of diamond for device-level thermal management
The efficiency and reliability of power and RF devices are not only limited by the electronic properties of the
material but also by their thermal management [326], as mentioned in section 2.3.2.1. At the device level,
Joule heating occurs in the channel due to increased power density and switching speeds. As a result, device
performance can suffer from high temperatures which can eventually result in premature failure. While
developing diamond-based devices can be a solution due to diamond’s excellent thermal and electronic
properties, enormous research efforts and progress are still needed to achieve high-performance devices. On
the other hand, heterogeneous integration of diamond can serve as a heat spreader solution for more mature
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Figure 22. (a) The temperature rise 0.5 µm from the T-gate edge for GaN-on-SiC and GaN-on-Diamond HEMTs measured using
Raman thermography and shown to increase with increasing power density; (b) the temperature across GaN, the interface, and
diamond were simulated and showed that minimizing the thermal resistance at the interface can more significantly reduce the
temperature in GaN than simply increasing the thermal conductivity of diamond [329].
Figure 23. (a) Backside approach for diamond integration to GaN. The SiC and nucleation layer are removed, and the GaN
epilayer is thinned before bonding to diamond [330]; (b) topside/all-around PC diamond integration by MPCVD diamond
growth above the substrate [331].
material technologies like GaN as well as other emerging UWBG materials such as Ga2O3and AlGaN which
have inferior thermal properties [327,328]. GaN technology, more specifically AlGaN/GaN HEMTs at its
current stage, has already penetrated the high-frequency, high-power device market for power amplifiers.
Thus, there is particularly high interest in device-level cooling for these structures to enhance their power
output. Due to silicon carbide’s relatively high TC, GaN-on-SiC technology is customarily used for power RF
devices. As diamond possesses a significantly higher TC, Pomeroy et al demonstrated that GaN-on-diamond
could yield a 40% decrease in peak channel temperature in comparison to GaN-on-SiC AlGaN/GaN HEMTs
based on a combination of Raman thermography measurements and thermal modeling (figure 22) [329]. To
implement such a diamond-based thermal management strategy, there are two primary approaches as
illustrated in figure 23: backside diamond substrate bonding and PC CVD heteroepitaxial diamond growth.
Several works have shown the feasibility of GaN to diamond bonding at lower annealing temperatures of
150 ◦C–180 ◦C using 15–40 nm thick undisclosed/Si-based adhesion interlayers [330,332]. However, the
thermal boundary resistance (TBR) of the GaN/diamond interface including the adhesion layer can become
a dominating source of thermal resistance as displayed in figure 22(b) [329]. To take full advantage of a
diamond heat spreader, a low diamond to substrate TBR is required in addition to a high diamond TC. More
recently, the process of surface-activated bonding (SAB) at room temperature under high vacuum was
developed (figure 24) [333]. Using this technique resulted in a relatively low GaN/diamond interface TBR of
∼11 m2K (GW)−1with a 4 nm bonding sputtered Si bonding layer [334]. While this method requires a
specialized tool, a more recent study has established a low temperature, easy-access method in which no
pre-deposited interlayer is needed [335]. In this process, a GaN substrate first underwent HCl chemical
treatment and the diamond NH4OH/H2O2treatment. Then, a 2 h, 200 ◦C, 1 MPa bonding was sufficient to
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J. Phys. Mater. 7(2024) 022003 K Woo et al
Figure 24. (a) A room temperature surface-activated bonding process assisted by Si nanolayers for GaN/diamond yielding an
interface free of nanovoids as shown by TEM imaging [333]; (b) a 3 inch GaN-on-diamond wafer with fabricated HEMTs using
low temperature bonding [332].
Figure 25. (a) Residual stress as a function of PC diamond film thickness; (b) cross-section schematics and SEM micrographs
showing the transformation of diamond grains from a columnar structure to more isotropic [337].
bond the two materials. TEM images showed the formation of a 3 nm amorphous layer, which was predicted
to produce a low TBR due to its thinness, although it has not been measured.
In addition to studying diamond thermal management from a material perspective, diamond heat
spreading technology must also demonstrate integration without degradation of the device, show an
operational temperature decrease, and ultimately enhance device performance and reliability. Using low
temperature bonding methods to PC diamond substrates, several groups have shown device-first transfer
technology of GaN HEMTs. Chao et al maintained a high-performance HEMT with a maximum output
power density of 11.0 W mm−1at 10 GHz and a PAE of 51% following the transfer to diamond [330].
Furthermore, IR imaging showed three times higher dissipated power in the same active area of a
GaN-on-diamond HEMT in comparison to that of GaN-on-SiC. Liu et al later successfully demonstrated
3 inch GaN-on-diamond HEMTs with >80% yield and measured a 50 ◦C decrease in peak channel
temperature (from 241 ◦C to 191 ◦C) at 10 W mm−1[332]. With these promising device-level results,
similar studies must continue as advancements in the thermal properties of diamond heat spreader
technology are made.
Alternatively, a topside PC diamond heat spreader can be advantageous since the diamond can be
integrated closer to the channel and more effectively transfer heat away from the channel hot spot.
Furthermore, it has increased potential for scalability since it is not limited by the diamond substrate size. To
implement this approach, heterogeneous epitaxial growth of diamond must be well-understood. First, to
nucleate diamond grains on foreign substrates, a seeding process using diamond nanoparticles is performed.
After, the seeded substrate is placed in a hot filament or MPCVD chamber for growth at 400 ◦C–1000 ◦C,
relying on the same chemistry as that of substrate growth described in section 4.2.1. An important parameter
when growing diamond on a foreign substrate is the residual stress due to a coefficient of thermal expansion
(CTE) mismatch between the two materials [336]. Since diamond has a very low CTE of ∼1.1 ×10−6K−1, it
typically contracts less than the substrate while cooling down from growth temperatures, causing
compressive stress to form in diamond. The magnitude of stress increases with growth thickness
(figure 25(a)), eventually causing the diamond to delaminate from the substrate [337]. This limits the
thickness of PC diamond that can be grown on foreign substrates.
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Figure 26. Lower temperature in the channel was measured for all-around diamond devices using multiple methods: (a) I–V
thermometry, (b) thermoreflectance imaging, and (c) gate-resistance measurement [331].
Depending on the growth parameters (e.g. gas pressure, plasma power, surface temperature, CH4%, etc),
seeds may grow in the vertical and lateral directions at different rates. Figure 25(b) shows how the change in
the growth parameters can transform the columnar structure into a more-isotropic structure [338]. Because
one primary drawback of heteroepitaxial PC diamond growth on GaN is the reduced TC in comparison to
SC diamond, the formation of large, isotropic diamond grains is crucial. Developing more isotropic growth
enhances in-plane phonon transport by reducing scattering sites at the grain boundaries, thus increasing the
effective TC and overall capability for device cooling. For example, the more isotropic diamond grains grown
by Malakoutian et al compared to others resulted in a relatively higher TC of ∼648 W m−1K−1for a 2 µm
thick epilayer [338]. Furthermore, there are tremendous efforts in reducing heteroepitaxial diamond-on-GaN
TBR for the same reasons highlighted earlier in this section. Zhou et al and Yates et al showed that using a
SiNxinterlayer between diamond and GaN produced an average TBR of 6.5–9.5 m2K (GW)−1, while using
an AlN interlayer averaged 15.9–18.2 m2K (GW)−1[339,340]. In another work, Malakoutian et al, reported
the lowest measured TBR between diamond and GaN ∼3.1 m2K (GW)−1by using a 1 nm SiNxinterlayer
[338], indicating that the heat transfer will not be hindered significantly at the interface.
Because typical diamond growth takes place under high temperatures (HT), between 600 ◦C and
1000 ◦C, diamond integration with many semiconductor technologies will inevitably damage the device or
substrate material. As a result, there have been many efforts to reduce the growth temperature for
compatibility with low thermal budget materials and processes. Low temperature (LT) diamond growth has
been reported in a temperature range from 100 ◦C to 500 ◦C. The growth of a high-quality PC diamond at
back end of line compatible temperature, 400 ◦C, was achieved by modifying the gas chemistry at different
nucleation stages. A sharp sp3Raman peak (full width at half maximum ≈6.5 cm−1) and high phase purity
(97.1%), like that of HT-diamond (>98%) were measured in the near-isotropic PC diamond [341].
Furthermore, the LT diamond exhibited a relatively high in-plane and cross-plane TC of ∼300 W (m·K)−1,
and a TBR as small as 5 m2K (GW)−1. The results of these studies highlight the feasibility of diamond
integration with various semiconductor technologies and open a path for heat spreading solutions for
practical adoption.
By using the LT diamond growth technique, Soman et al demonstrated the cooling effect of an integrated
all-around PC diamond structure on the topside of a GaN HEMT. The thermal resistance between the
device’s active region and heat sink was reduced using PC diamond integration, ultimately resulting in a
channel temperature decrease of >70 ◦C at 25 W mm−1power operation shown using I–V thermometry
[331]. The thermal benefits were further confirmed using thermoreflectance and gate-resistance
measurement techniques illustrated in figure 26. As the inefficiency due to heating is a universal problem in
electronics, particularly in high-frequency and high-power switching, continued research in diamond
integration for thermal mitigation has the potential to highly impact the field.
Among the emerging UWBG semiconductors, β-Ga2O3, discussed later in section 5, has already
demonstrated great potential for power device technologies while offering a low-cost method for
large-diameter wafer growth. Nonetheless, a notable drawback of this material is its markedly low,
anisotropic TC ranging from 11 to 27 W m−1K−1. As a result, there is particularly high interest in
employing diamond as a heat spreader for Ga2O3. A few key studies have been published that parallel the
integration approaches undertaken in GaN. Low-temperature bonding of Ga2O3and diamond was achieved
by Matsumae et al by first OH terminating both diamond and Ga2O3using H2SO4/H2O2and oxygen plasma
irradiation, respectively. The contacted materials were then annealed at 250 ◦C for hydrophilic bonding to
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Figure 27. (a), (b) Exfoliated 10 µmβ-Ga2O3bonded to diamond and the TEM image of its interface [342]; (c), (d)
MPCVD-grown diamond on a 100 nm SiO2interlayer on β-Ga2O3, yielding an average grain size of 400 nm [327].
Figure 28. (a) A vertical extrinsic diamond PCSS excited by 532 nm light; (b) the band diagram representation of the mechanism
by which electrons are excited from the nitrogen deep donor level in diamond to the conduction band in response to 532 nm light
[349].
take place (figures 27(a) and (b)) [342]. Additionally, PC diamond heteroepitaxial growth on β-Ga2O3
substrates was shown using a relatively thick SiO2protective interlayer that prevented substrate damage and
enabled uniform diamond nucleation [327,343]. As illustrated in figures 27(c) and (d), at lower
magnifications, the diamond-on-Ga2O3film exhibits remarkable uniformity, and at high magnification
SEMs, dense PC diamond was observed [327]. These results mark a significant step towards device-level
thermal management for β-Ga2O3.
4.3.4. Photoconductive semiconductor switching
Photoconductive semiconductor switches (PCSS) are optically controlled electronic devices that are desired
for their high voltage, high speed, and jitter-free operation [344]. This is achieved by modulating the
conductivity of a semiconductor substrate with a light energy source. These devices are especially effective in
pulsed power technology, such as radar, particle acceleration, and pulsed high-power lasers. Furthermore, as
there are increased efforts toward electrification, developing safer mechanisms for making and breaking high
power circuits is a priority. By decoupling the trigger from the circuit with an optical source, the chances of
false triggering are reduced and more simple and resilient circuits can be enabled [345]. One of the main
issues of photoconductive switches is their short lifespan resulting from voltage and current overloads as well
as thermal runaway effects at high-power levels [344]. The use of diamond and other UWBG semiconductors
to fabricate PCSS devices could mitigate some of these issues owing to their superior material properties.
Past studies have shown photoconductivity in intrinsic diamond by UV-band excimers in high electric
fields up to 0.7 MV cm−1,>10 kV conditions, and with picosecond to nanosecond response times
[346–348]. In contrast to intrinsic PCSSs, which depend on high photon energies above the bandgap
(band-to-band excitation), extrinsic PCSS operates with below bandgap photon energies due to the
excitation of carriers from dopants and defect levels as illustrated in figure 28(b). This enables PCSS
functionality with more accessible sub-bandgap excitation sources in the visible or infrared range while
maintaining the desirable properties of diamond. Nitrogen-doped diamond-based PCSSs have shown
nanosecond pulsed responses to 532 nm light by exciting an electron from the deep defect level (1.7–2.0 eV)
of nitrogen into the conduction band [345,349]. Since diamond’s nitrogen dopants are largely inactivated at
room temperature, making ohmic contacts is challenging for PCSS devices. However, Woo et al showed that
the contact resistivity is reduced when the electrodes are under illumination which enabled a high Ion/Ioff
ratio (>1011 at 33 kV cm−1in response to 0.8 mJ, 10 ns pulsed, 532 nm light). The responsivity of
nitrogen-doped diamond to 532 nm light was found to be less than that of diamond UV light, but
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comparable to the responsivity of SiC and GaN extrinsic PCSSs [349]. On the other hand, boron doped
diamond was found to be responsive to both 532 and 1064 nm light due to its lower activation energy
(0.37 eV). While its large off-state conductivity renders it a poor candidate as a switch on its own [345],
photoexcitation of boron dopants may still lend itself to other optically triggered electronic devices. Further
studies to increase the quantum efficiency of the PCSS and explore the use of other defect states will greatly
contribute to the practicality of light-triggered devices in diamond.
5. Beta-gallium oxide (β-Ga2O3)
5.1. Material properties
Five types of Ga2O3polymorphs were reported in 1952, denoted as α,β,γ,δ, and ε, respectively. However,
recent high-resolution structural characterizations revealed that a transient κ-phase polymorph could form
an ordered subgroup in the ε-phase, and an ε/κphase could coexist instead of a pure-phase Ga2O3
polymorph [350,351]. Among all the five polymorphs, β-Ga2O3is the only thermodynamically stable phase
and therefore, the most extensively studied. In this review, the discussions will only focus on the material
properties and device applications of β-Ga2O3.
The most attractive merit of β-Ga2O3is its high critical field due to its large bandgap of 4.9 eV. Based on
the empirical relationship between the critical field and the material’s bandgap, a critical field as high as
8 MV cm−1was predicted for β-Ga2O3theoretically [3,352]. However, almost all the experimental results
demonstrated a premature destructive breakdown for β-Ga2O3devices due to the field crowding at the edge
of the gate dielectric or the anode electrode. The highest average critical field reported was around
6 MV cm−1in vertical SBDs [353,354], and no avalanche was reliably observed in a β-Ga2O3device.
The electron mobility at room temperature for the doping range of 1015–1016 cm−3is reported to be
around 150–200 cm2(V·s)−1[355–357], and is mainly limited by the longitudinal optical phonons in the
β-Ga2O3[358]. The saturation velocity of electrons in β-Ga2O3was calculated to be around
1–2 ×107cm s−1[359], which is sufficient for many high-frequency applications. Unfortunately, due to the
flat valence band maximum in β-Ga2O3, leading to a heavy hole effective mass, the mobility of holes is
expected to be very low and nearly no measured values have been reported.
Another one of the main drawbacks of β-Ga2O3is its low TC, posing another challenge for its
high-power applications. The extracted TC of β-Ga2O3is 0.27 W (m·K)−1along the [010] direction and
0.11 W (m·K)−1along the [99] direction [360]. Since these values are only 1/10 of the values for SiC and
GaN, more efficient thermal management for Ga2O3devices is demanded.
5.2. Growth and doping
5.2.1. Bulk substrate growth
One of the distinctive features of β-Ga2O3among U/WBG materials is that its native substrates can be grown
via the melt growth method. Consequently, mass production of β-Ga2O3substrates with large wafer sizes,
high structural quality, and low manufacturing costs is more feasible. The β-Ga2O3substrates can be grown
from various melt growth methods: float zone [361–363], Czochralski [364,365], vertical Bridgman, and
edge-defined film-fed growth (EFG) [366], pictured in figure 29. Among these methods, the EFG growth
method shows great potential in offering large-diameter β-Ga2O3substrates. 4 inch single-crystalline
β-Ga2O3substrates have been successfully grown via the EFG method with a low dislocation density of
103–104cm−2and a surface roughness of 0.1 nm [367]. To date, 2 inch β-Ga2O3substrates are commercially
available to the public.
5.2.2. Epitaxial layer growth
Like other compound materials in this review, several familiar techniques: MBE, HVPE, and MOCVD are
often used for the epitaxial growth of Ga2O3. MBE, which can offer high-purity growth with precise control
of thickness, has been the most commonly used technique for thin film Ga2O3growth at the beginning of its
research and development [370–372]. The growth typically occurs by oxidizing the supplied Ga atoms using
ozone or oxygen radicals [373,374]. Intentional dopants, such as Si, Sn, and Ge can be incorporated during
MBE growth. However, it is difficult to achieve a doping density on the order of 1016 cm−3or less due to the
oxidization of the dopant source by background O species during the growth [375].
HVPE growth of Ga2O3was demonstrated in 2014 by using GaCl and O2as precursors [376]. Like HVPE
growth of GaN, the GaCl is formed by the reaction of gallium metal source and Cl2gas at 850 ◦C in a source
zone first and then transported to the growth zone and reacted with O2. Here, SiCl4is commonly used as an
n-type dopant source. The growth rate of HVPE can reach up to 20 µm per hour without degrading the film
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Figure 29. Bulk β-Ga2O3crystals grown by (a) the Czochralski method [368] and (b) the edge-defined film-fed growth (EFG)
[369]; (c) a 4 inch β-Ga2O3substrate with a surface orientation of [2¯01] grown by EFG method [369].
quality. A low unintentional doping of 1013 cm−3has been achieved by HVPE growth and intentional doping
density in the range of 1015–1019 cm−3can be accurately controlled by adjusting the flow of SiCl4[377].
MOCVD is well established in several other compound semiconductors, as mentioned earlier, and can
mass produce high-quality epitaxial films. Gallium precursors, such as trimethylgallium (TMGa) and
triethylgallium (TEGa), and high-purity O2are typically used for MOCVD growth of Ga2O3. At the
beginning of development, MOCVD growth of Ga2O3faced challenges of low growth rates, high background
carrier concentrations, and low electron mobilities [375]. Thanks to the tremendous efforts in optimizing the
growth conditions, the structural and electrical properties of Ga2O3film grown by MOCVD have been
significantly improved over the recent years [378–382]. Another unique advantage of MOCVD growth is its
ability to produce a β-(AlxGa1−x)2O3/Ga2O3heterostructure [375,383,384], which constitutes an
important architecture in Ga2O3-based RF applications.
While the aforementioned growth methods are currently the leading techniques and attract significant
research interest in Ga2O3epitaxy, additional growth methods, including low pressure chemical vapor
deposition (LPCVD) [385–388], mist chemical vapor deposition (Mist-CVD) [389–391], liquid injection
metalorganic chemical vapor deposition (LI-MOCVD) [351,392], and pulsed laser deposition (PLD) [393,
394], have offered epitaxial Ga2O3films of comparable film qualities with the benefits of relatively low
deposition temperatures, large carrier concentration ranges, high deposition rates and relatively inexpensive
deposition equipment. Lastly, heteroepitaxy of Ga2O3device structures on more thermally conductive
foreign substrates for heat mitigation employs epitaxial growth methods described in this section. However,
more specific works are further described in section 5.3.3.
5.2.3. Doping
Silicon (Si), Tin (Sn), and Germanium (Ge) are commonly used as donors in β-Ga2O3[395]. At room
temperature, the donors show a high activation ratio due to the shallow donor states, typically around
30 meV below the conduction band [396–400]. These dopants can be incorporated into the β-Ga2O3
through in-situ growth, ion implantation, or diffusion method. The conductivity of the n-type β-Ga2O3can
be well modulated by controlling the donor concentration, within the range of 1015–1020 cm−3.
In contrast to the ease and success in achieving n-type doping in β-Ga2O3, p-type doping in β-Ga2O3
has evaded researchers and has become a primary limitation in the rapid development of various β-Ga2O3
devices [3,375]. Several elements, including Mg, and N, were reported to serve as deep acceptors in
β-Ga2O3, though with an activation energy larger than 1 eV [401,402]. Besides, the first principle
calculations predict a very flat valence band, leading to a large hole effective mass and low mobility [403,
404]. Moreover, self-trapping of holes limits the free hole conduction in β-Ga2O3due to the local lattice
distortion [405–407]. The combination of these factors contributes to the difficult nature of achieving
well-behaved hole conduction. Recently, Chikoidze et al, reported that undoped β-Ga2O3after an oxygen
anneal exhibited p-type nature above 500 ◦C. A free hole concentration of around 1017 cm−3(mobility
∼0.4 cm2(V·s)−1) was measured and attributed to the large formation energy of the oxygen donor vacancies
[408,409]. These findings help the community understand the mechanism behind the carrier formation and
potentially shed light on achieving better p-type conductivity suitable for practical use in Ga2O3.
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Figure 30. (a) Schematics of the fabricated NiO/Ga2O3heterogeneous PN diodes; (b) SEM image of the cross-sectional anode
field plate region; (c) radius-dependent forward current-voltage-resistance curves for a drift layer thickness of 13 µm; (d)
radius-dependent reverse breakdown curves for a drift layer thickness of 13 µm; (e) hole lifetime dependence on the forward
injection current, measured in reverse recovery transient behavior [354].
5.3. β-Ga2O3device and applications
5.3.1. High power devices
5.3.1.1. SBDs
Ga2O3SBDs were first demonstrated on native n-type Ga2O3substrates, due to the absence of suitable
epitaxial growth methods for thick n-drift layers on Ga2O3substrates. In 2013, a Ga2O3SBD fabricated on a
bulk (010) substrate grown by the float zone method was reported [410]. A Schottky barrier height of
1.3–1.5 eV was extracted for the Pt contact, and the SBD exhibited a near-unity ideality factor, indicating
high crystal quality and good Schottky contact properties. The diodes showed a 150 V breakdown voltage
and a high on-resistance of 7.85 mΩ·cm2, which was attributed to the low conductivity of the bulk
substrates. Later, with the advancement of HVPE growth, a 7 µm-thick Si doped drift layer with doping
concentration around 2 ×1016 cm−3was grown on highly Sn-doped (2.5 ×1018 cm−3) (001) native Ga2O3
substrates. The fabricated SBDs showed a breakdown voltage of 500 V with an improved on-resistance of
3 mΩ·cm2[411]. Catastrophic breakdown occurred in the devices due to the electric-field concentration at
the edge of the anode, requiring efficient edge termination to suppress the peak electric field and reduce the
leakage current. Several approaches, such as field plating [412–414], junction termination extensions
[415–417], and trench metal–insulator–semiconductor (MIS) structures [418,419], have been proposed and
prototyped in Ga2O3SBDs. By deploying a self-aligned field plate with a deep trench filled with thick SiO2, a
6 kV SBD with a specific on-resistance of 3.4 mΩ·cm2was successfully fabricated. This device offered a high
BFOM of 10.6 GW cm−2[353] and exceeded the 1D unipolar limit of SiC and GaN.
5.3.1.2. Heterogeneous PN diodes
Though effective p-type β-Ga2O3is still under development, the use of heterogeneous PN structures that
employ NiO as the p-type material establishes another route for achieving high voltage diodes [420–425].
The high turn-on voltage, which leads to conduction losses, is characteristic of homogeneous PN structures
in WBG materials. However, the band offset of NiO can reduce the threshold voltage, partially resolving this
issue [354]. Recently, Zhang et al reported a NiO/Ga2O3heterogeneous PN diode by combining Mg
implantation termination and field plating architectures with schematics and SEM cross-sections shown in
figures 30(a) and (b). These devices produced an 8.32 kV breakdown voltage and the highest BFOM of
13.2 GW cm−2among all UWBG power diodes to date [354]. The reverse recovery behavior of the fabricated
heterogeneous PN diodes was measured, and the hole lifetime was determined to be 5.4–23.1 ns
(figure 30(e)), yielding a mobility of 1.9–8.3 cm2(V·s)−1. Despite the difficulties in observing free hole
conduction in Ga2O3as discussed in section 5.2.3, this result indicates that holes can be manufactured in
Ga2O3via hole injection, and their presence is not limited by the self-trapping effect.
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Figure 31. (a) Schematical view of lateral Ga2O3MOSFET based on vacuum annealing with a composite field plate and SU-8
encapsulation layer; (b) breakdown characteristics for the device, the highest breakdown voltage was 8558 V for a 60 µm channel
length grown by MBE; (c) comparison of the on-state resistance with vacuum annealing for the channel grown by MOCVD (blue
line) and grown by MBE (red line), and without vacuum annealing grown by MBE (gray line); (d) comparison of the breakdown
voltage with vacuum annealing for the channel grown by MBE (blue line) and MOCVD (red line), and without vacuum
annealing grown by MBE (gray line) [434].
5.3.1.3. MESFETs and lateral MOSFETs
MESFETs were successfully fabricated on Mg-doped semi-insulating Ga2O3substrates in 2011 [352]. A
300 nm thick Sn-doped channel layer was grown by MBE and a Pt/Ti/Au metal stack was deposited as the
Schottky gate. The device showed an on–off ratio of 104and a decent three-terminal breakdown voltage of
250 V. However, the unpassivated surface led to a small gate leakage, and the devices suffered from low
on-state current due to the high contact resistance of the source/drain electrodes. Later usage of Si ion
implantation or diffusion at the source/drain electrode significantly reduced the contact resistance to the
order of 10−5Ω·cm2[426,427] and thus resolved a significant limitation of the on-state current for Ga2O3
transistors.
MOSFETs have been studied to improve the performance of Ga2O3transistors. Depletion-mode Ga2O3
MOSFETs have been demonstrated with an ALD Al2O3layer as the gate dielectric as well as the surface
passivation layer to reduce surface leakage [428]. On the other hand, a SiO2dielectric/Ga2O3interface was
reported to have a large conduction band offset and low interface state density [429], offering an
enhancement-mode Ga2O3MOSFET using a Pt gate [430]. These devices showed a breakdown voltage of
400 V without a field plate structure, and the integration of field plate structures enabled a much higher
breakdown up to 8 kV [431–433]. Figure 31(a) depicts the device schematic of a lateral Ga2O3MOSFET with
a composite field plate design, offering a record-high breakdown voltage of 8.56 kV [434]. The authors
reported that vacuum annealing significantly reduced the on-resistance by recovering the surface damage
caused by a reactive-ion etching process during fabrication. The on-resistance was reduced by one-order of
magnitude while excellent blocking capability was maintained.
5.3.1.4. Vertical transistors
Vertical Ga2O3transistors are favorable in power applications due to their high volume utilization and high
power density. Using a fin-shaped channel in vertical transistors (FinFET), as pictured in figure 32(a),
removes the need for a p-type material. This structure can also avoid the low effective channel mobility
caused by etching damage and interface states in MOSFETs. The demonstration of a 2.6 kV transistor with an
on-resistance of 25.2 mΩ·cm2[435] promoted continued interest and development of FinFET technology in
Ga2O3. Although FinFETs have exhibited a high breakdown voltage in Ga2O3, the complicated and costly
fabrication process with potentially low device yield is a concern for the technology.
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J. Phys. Mater. 7(2024) 022003 K Woo et al
Figure 32. Schematical view of different architectures of vertical Ga2O3transistors: (a) FinFET [435]; (b) current aperture vertical
MOSFETs with nitrogen implanted blocker layer [438]; (c) vertical transistor with a diffused barrier (VDBFET) [441]; (d)
U-shape trench gate MOSFET with nitrogen ion implantation [442].
Though p-type Ga2O3remains a challenge for the whole community, n-type conductive Ga2O3can be
converted to insulating materials by oxygen annealing [436,437] or by Mg/N implantation or diffusion
[438–440]. This can be useful for forming effective current blocking layers in developing vertical transistors.
Wong et al reported the first Ga2O3CAVET (figure 32(b)) with a Mg implanted blocking layer [439].
However, the devices showed relatively high leakage and poor gate modulation. A possible reason was the
diffusion of Mg caused by high temperature annealing used to repair crystal damage after implantation.
Later, the same group reported on an N implantation based Ga2O3CAVET [438], demonstrating a
breakdown voltage of 253 V with a decent on–off ratio of 107, but a large specific resistance of 135 mΩ·cm2.
In contrast to the use of implantation technology, Zeng et al utilized an Mg-diffusion process (figure 32(c))
to form a current blocking layer [441], thus avoiding unwanted Mg diffusion during the post-annealing
process. The prototype exhibited normally-off operation and a high on–off ratio of 108. Though the
breakdown voltage was limited to 73 V, this novel diffusion doping method opens an alternative route toward
developing vertical Ga2O3transistors.
Similar to SiC and GaN, the U-shaped trench MOSFET (UMOSFET) (figure 32(d)) has also attracted
great research interest and was successfully fabricated based on oxygen-annealed and N-implanted channel
layers [442,443]. The nature of the MOSFET made it easy to achieve normally-off operation. Recently, a
UMOSFET with a N-implanted current blocking layer exhibited a breakdown voltage of 455 V with a low
on-resistance of 10.4 mΩ·cm2[442].
5.3.2. RF devices
Green et al reported the first RF measurement data in Ga2O3employing a lateral MOSFET architecture with
a 180 nm MOVPE-grown Si-doped epitaxial layer on semi-insulating Ga2O3substrates. A gate recess was
utilized to reduce the channel thickness to 90 nm [444]. Their devices delivered an fTof 3.3 GHz and a fmax
of 12.9 GHz, as well as a continuous wave mode output power of 0.23 W mm−1and PAE of 6.3% measured
at a drain voltage of 25 V at 800 MHz. Later, Singh et al proved that self-heating was a dominant factor
limiting the performance of Ga2O3RF devices [445]. By adopting a pulsed mode measurement method, the
device produced 0.13 W mm−1at 1 GHz with a higher PAE of 12%. This finding urges more effective
thermal management strategies to address the low TC issue for Ga2O3. In addition, the pulsed IV
measurements indicated that drain-dispersion, likely caused by traps located either at the surface of the gate
dielectric or gate-oxide–semiconductor interface, limited the RF output power as well [446].
Gate length scaling can boost the frequency of RF devices; however, it is limited by the thickness of the
channel. A high gate-channel aspect ratio (gate length over gate-to-channel distance) needs to be maintained
to suppress the short-channel effect. By growing a 65 nm thick channel layer with a carrier concentration of
33

J. Phys. Mater. 7(2024) 022003 K Woo et al
2×1018 cm−3and decent mobility of 90 cm2(V·s)−1, Chabak et al further scaled down the gate length to
140 nm, achieving an fT/fmax of 5.1/17.1 GHz [447]. Kamimura et al utilized shallow Si implantation to
define a thin channel to maintain the high aspect ratio. Their devices offered a high fT/fmax of 10/27 GHz
[448]. Similarly, the growth of a delta-doped Si layer is another way to achieve high sheet charge density and
better confinement in the channel, thus enabling an fT/fmax of 27/16 GHz [449]. The (AlxGa1−x)2O3/Ga2O3
heterostructure is an alternative architecture that can achieve better carrier confinement and reduced
effective channel thickness [450,451]. High carrier densities between 1012 and 1013 cm−2have been reported
in (AlxGa1−x)2O3/Ga2O3modulation-doped transistors (MODFET) with enhanced carrier mobilities
[452–456]. A record-high fT/fmax of 30/37 GHz has recently been reported in (AlxGa1−x)2O3/Ga2O3
MODFETs [457].
5.3.3. Thermal management for Ga2O3devices
Ga2O3is notorious for its low TC and will especially suffer from self-heating. Self-heating not only degrades
the reliability and lifetime of a device but also limits its electrical performance. Several cooling strategies have
been reported for thermal management at the device level in Ga2O3, including heteroepitaxial channel
grown on foreign substrates with high TC, wafer bonding to high-thermal-conductivity substrates, and
integration of heat spreading layers in close proximity to the active device areas. Details regarding
diamond-based thermal management for β-Ga2O3were discussed in section 4.3.2.
Various studies have reported thin Ga2O3epitaxial growth on SiC [458,459], AlN [460], and diamond
substrates [461,462] due to their much higher thermal conductivities. The TC of an 81 nm thick β-Ga2O3
grown on 4H–SiC substrate was measured to be 3.1 ±0.5 W (m·K)−1and the thermal boundary
conductance between β-Ga2O3/SiC interface was 140 ±60 MW (m2·K)−1[459]. Despite the promising
results shown by thermal characterization and device simulation, experimental demonstration of an active
device of Ga2O3on foreign substrates without degrading the electrical performance is yet to be shown.
Besides the direct growth of Ga2O3on foreign substrates, the integration of β-Ga2O3with highly
thermally conductive substrates has also been reported through ion cutting [463,464] and fusion bonding
processes [465]. A thermal boundary conductance of 60–130 MW (m2·K)−1between the β-Ga2O3/SiC
interface formed via the ion cutting process was reported [464]. Minimizing the thermal boundary resistance
and Ga2O3substrate thinning is key in facilitating efficient heat removal. A Ga2O3SBD on a thinned-down,
100 µm-thick bulk substrate showed a significant reduction in junction-to-case thermal resistance by 30%
compared to the reference device on 250 µm-thick substrates [466], and further substrate thinning to less
than 50 µm with the integration of a backside heat sink are predicted to offer further improvements of heat
transfer [467].
6. Conclusion
Over the course of recent decades, GaN-based electronics have undergone extensive exploration for various
applications, including optoelectronics, high-power devices, and high-frequency electronics. This surge in
interest can be attributed to GaN’s exceptional material properties. Substantial progress has been achieved in
pushing the boundaries of device performance, encompassing both fundamental research and advancements
in industrial processes. This continuous improvement in the fields of physics, materials science, and
manufacturing processes has expanded the horizons for WBG materials, ushering in new possibilities and
catalyzing numerous research breakthroughs, particularly in the realm of UWBG technology. To quantify the
progress achieved in the domain of U/WBG materials, figure 33 has been plotted as a benchmark, utilizing
Baliga’s figure of merit, specifically the relationship between Ron and breakdown voltage, as a measure of
performance for power devices. Remarkable advances have been made by researchers, resulting in the
development of kilovolt-class diodes and transistors across all the materials discussed within this review. This
accomplishment underscores the immense potential of these U/WBGs for high-power applications.
In the field of RF applications, GaN HEMTs have demonstrated outstanding performance metrics and
have successfully transitioned into commercialization for applications within the X-Ka band. Conversely, the
landscape for UWBG materials is still in its nascent stages of development, as depicted in figures 34(a) and
(b). These figures vividly illustrate that the state-of-the-art power and RF performance across various UWBG
materials significantly lags behind that of GaN.
In the final part of this review article, we are choosing a few common research directions that will
significantly impact the WBG to UWBG transition.
Substrates serve as the fundamental building blocks for semiconductor technology, forming the critical
foundation upon which it is constructed. The issue of scalable substrates is a pervasive challenge across all the
materials under discussion here. Bulk GaN devices have garnered significant research interest due to their
potential for higher performance and enhanced reliability. However, the availability of suitable substrates
34

J. Phys. Mater. 7(2024) 022003 K Woo et al
Figure 33. BFOM unipolar limit and experimental data for (a) two-terminal and (b) three-terminal devices. References for (a)
GaN SBDs: [61,67,69,72,73,468,469]; GaN PNDs: [79–82,89,90,470]; GaN JBS, SJs: [92,93,95]; AlGaN/AlN: [214,236,237,
250,251,471]; diamond: [281,287,292–294,302,472–475]; Ga2O3SBDs: [353,412,413,415,417–419,476]; Ga2O3/NiO PNDs:
[354,421,423,424,477] and (b) lateral GaN: [114,120,128,478,479] and references therein [480], and references therein;
vertical GaN: [131,134,135,139,141,145,147,481]; AlGaN: [215,216,233,239,482]; diamond: [309,312,483–485]; lateral
Ga2O3: [432–434,486,487] Ga2O3vertical [435,438,442,443,488,489].
Figure 34. State-of-the-art RF performance: (a) fmax vs fTand (b) Pout vs frequency of U/WBG transistors. References for (a) GaN
HEMTs: [490–501]; AlGaN: [217,242–248,502]; diamond: [321–324,503–510]; Ga2O3: [444,448,449,511] and (b) GaN
HEMTs: [157,159,160,164–166,171,176,178,490,512]; AlGaN: [217,242,247,248]; diamond: [319,320,322,324,503–508,
325,513,514]; Ga2O3[444–446].
remains constrained by both size and cost limitations. For instance, the cost of a 2 inch bulk GaN substrate
remains prohibitively high, and the commercial availability of substrates larger than 4 inches remains a
formidable challenge as of the present date. The development of electrically conducting and optically
transparent AlGaN substrates is still in its infancy, and in the case of diamond substrates, typical MPCVD
growth methods limit their size to less than 1 cm. Although ongoing efforts in the realm of novel growth
methods have resulted in the production of larger substrates, the demonstration of large-diameter bulk GaN,
AlN, AlGaN, and diamond substrates with both low defect densities and affordable manufacturing costs
remains a formidable hurdle for researchers to overcome.
While it is widely recognized that achieving improved doping control and faster growth rates is
imperative for all the materials under discussion, we believe that a pivotal area of research lies in selective
area doping within UWBG materials. Selective area doping has the potential to yield remarkable
advancements in many device concepts. Generally, due to the substantial bandgap in UWBG materials, the
activation of dopants to attain high carrier densities has presented a persistent challenge. The overall
proficiency of doping through innovative techniques such as light-assisted doping and selective area
regrowth methods holds the promise of facilitating more effective device technology. To date, the absence of
reliable n-type and n+doping methods in diamond, coupled with the scarcity of p-type and p+doping
techniques in AlGaN and the absence of an effective p-type doping method in Ga2O3, hinders the creation of
properly designed PN junctions, the implementation of effective field termination techniques, and the
formation of robust ohmic contacts.
The success of ion-implantation can streamline various processes, offering simplifications with
significant implications. For instance, in devices like CAVET, the need for a complex regrowth step could
35

J. Phys. Mater. 7(2024) 022003 K Woo et al
potentially be reduced or entirely eliminated if ion-implantation can be consistently and effectively achieved.
Similarly, the creation of a deep p-well column, essential for fabricating superjunction structures, could
become a more practical manufacturing process if ion-implanted dopants could be reliably activated.
Therefore, it is imperative to continue researching doping techniques and alternative methods, some of
which have been discussed in this review.
For power electronics applications, achieving a robust and uniform avalanche effect in devices is of
paramount importance for safeguarding devices against the extreme conditions encountered in real-world
scenarios. This capability not only reduces the need for excessive over-design but also permits device
operation close to its material limits. While the avalanche phenomenon has been more consistently realized
in GaN PN diodes fabricated on native bulk GaN substrates, further data is necessary to fully comprehend
the mechanisms and harness their potential in practical applications. However, in UWBG materials, the
reliable observation and generation of the avalanche phenomenon remain elusive. This challenge can be
attributed in part to the immaturity of the materials and limitations in device architecture, underscoring the
need for the development of the physics governing avalanche in UWBGs.
High-k dielectric materials occupy a pivotal role in addressing the requirements of UWBG device
technologies. Gate dielectrics with superior electrical strength compared to the semiconductor channel are
essential for effective gate technology. These dielectrics must exhibit a very high critical electric field while
also providing substantial band offsets to minimize gate leakage. Given the limited space (in thickness)
available for the dielectric layer under the gate, the pursuit of high-kvalue materials becomes crucial. An
ideal dielectric should possess a large band offset, a high dielectric constant, low gate leakage, and minimal
interface traps to ensure the functionality and reliability of device technology. Insufficiently engineered
dielectric layers can significantly impact and even limit a device’s performance. Additionally, the emerging
branch of nitride ferroelectric gate stacks [515,516], not discussed in this article, is poised to acquire
substantial research interest in the coming decade.
Lastly, the concept of electro-thermal co-design is gaining prominence, particularly in GaN RF devices.
Elevated channel temperatures can degrade the mobility of the 2DEG and jeopardize device reliability under
high-power operation. Traditional thermal management techniques, such as heat sinks and appropriate
thermal interface materials at the package level, remain important. However, the heterogeneous integration
of PC diamond with other WBG materials and even silicon technology as a heat-spreading layer presents an
alternative approach to device-level cooling. Effective thermal management is essential for UWBG devices, as
they are expected to operate at higher voltages and significantly higher power densities, rendering them more
susceptible to thermal-related issues.
In summary, U/WBGs represent a highly fascinating and rapidly advancing domain, offering the
scientific community a vast array of research prospects in both materials science and device physics. The
anticipated range of applications is equally promising, following the path set by SiC and GaN.
Data availability statement
All data that support the findings of this study are included within the article (and any supplementary files).
Acknowledgments
This work was funded by ULTRA, an Energy Frontier Research Center (EFRC) funded by the U.S.
Department of Energy, Office of Science, Basic Energy Sciences under Award No. DE-SC0021230.
ORCID iDs
Kelly Woo https://orcid.org/0000-0002-8820-7975
Zhengliang Bian https://orcid.org/0000-0002-3097-9016
Maliha Noshin https://orcid.org/0000-0002-0736-6991
Rafael Perez Martinez https://orcid.org/0000-0001-6488-1247
Mohamadali Malakoutian https://orcid.org/0000-0002-5760-0408
Bhawani Shankar https://orcid.org/0000-0002-6674-3267
Srabanti Chowdhury https://orcid.org/0000-0001-8367-0461
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